Top Tech Jobs & Startup Jobs

Lead development, optimization, and transfer of advanced DRAM wet processes (cleans, etch, plating). Drive technology roadmaps, troubleshoot via root-cause analysis, collaborate cross-functionally and with vendors, and influence strategic process and tooling decisions to enable high-volume manufacturing.

Lead thin films process development for advanced DRAM: diagnose and resolve process issues, drive yield/cost/productivity improvements, validate and scale new processes/tools/materials, manage supplier quality and audits, and support product ramps.

Design and analyze digital and analog circuits for memory products. Lead layout (floor-planning, placement, routing), perform parasitic modeling, SPICE/Verilog simulation, design validation, reticle experiments and tape-out revisions. Collaborate with test, process integration, product engineering, and cross-functional teams to ensure manufacturability, reliability, cost, and time-to-market.

Lead R&D of AI-assisted EUV mask blank materials and processes (film stack design, deposition, etch, clean, patterning). Advance High-NA EUV readiness, optimize lithography performance and lifetime, translate lithography requirements into manufacturable mask solutions, perform DOE-driven data analysis to improve yield and reliability, and collaborate with OPC, design, lithography teams and suppliers to transition technologies into FEOL process engineering.

The Senior Package Design Engineer will design and optimize semiconductor packages, collaborating with cross-functional teams to enhance performance and manufacturability, while leading layout activities and contributing to standards and guidelines.

Lead development and integration of advanced DRAM device technologies. Design and run R&D fab experiments, analyze inline/parametric/probe data to identify variability and failures, collaborate cross-functionally to improve yield and performance, and apply AI-assisted analytics to accelerate root-cause identification.

Lead photolithography process development and wafer flow execution across shifts. Manage and mentor engineers, drive operational performance (cycle time, tool readiness), partner with integration, process and manufacturing teams to resolve issues, and apply AI/LLM-enabled approaches to improve decision-making and development efficiency.

Lead shift-based thin films process development and wafer flow, manage and mentor engineers, partner with process/integration/equipment teams, ensure data quality and resolve yield/defect issues, and drive operational improvements using data science and AI-enabled approaches.

Provide technical leadership to improve semiconductor equipment performance and capability across global fabs. Lead multi-site root cause analysis, enable node readiness, drive yield/defectivity improvements, standardize best practices, influence suppliers, optimize cost of ownership, and mentor engineering teams.

The role involves developing high-speed product signaling and power designs, mentoring junior staff, and engaging in cross-disciplinary collaboration.