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Supports EUV lithography and semiconductor manufacturing research through experiment design, cleanroom process coordination, metrology and process-data analysis, lithography performance evaluation, and process optimization. Projects may address photoresist performance, critical dimensions, registration, line width roughness, and patterning improvements. The intern communicates technical findings through reports and presentations, collaborates with multidisciplinary engineering teams, and applies AI-assisted tools to research and engineering workflows.

Develop and optimize plasma etch equipment for semiconductor memory products. Conduct experiments, create hardware and analytical techniques, analyze and document technical data, solve plasma etch hardware problems, and collaborate with cross-functional engineering teams while maintaining safety, quality, and compliance standards.

The Staff Design Engineer is responsible for designing and verifying digital circuits for memory products, collaborating with teams, and ensuring high performance and quality standards.

Design, simulate, validate, and optimize next-generation HBM architectures and circuit blocks. Perform pre- and post-layout analysis, timing and power verification, reliability reviews, tape-out support, and post-silicon bring-up. Collaborate with layout, verification, product engineering, test, process, packaging, and marketing teams to ensure manufacturable, reliable, cost-effective memory products.

Lead development and optimization of RET and OPC solutions for advanced memory lithography. Drive projects across R&D and manufacturing, analyze patterning issues, deploy simulation and process improvements, adopt AI-enabled methods, and mentor junior engineers to improve yield and manufacturability.

Leads the design, integration, and silicon delivery of analog and mixed-signal IP for HBM logic dies. Responsibilities include designing high-speed interfaces, clocking, SerDes, biasing, calibration, and power circuits; defining interfaces and power domains; conducting simulation and reliability analyses; guiding layout, floorplanning, matching, shielding, and EM/IR compliance; signing off layouts; optimizing designs for advanced nodes; and collaborating with digital, systems, packaging, and test teams.

The EUV Lithography Pathfinding Engineer will evaluate advanced lithography technologies, lead pathfinding activities, collaborate on roadmap requirements, and ensure implementation readiness for new patterning approaches.

Designs and owns high-performance analog and mixed-signal circuits for High Bandwidth Memory PHYs, including transmitters, receivers, clocking, SerDes, references, calibration, and power regulation. Performs pre- and post-layout simulation, variation and reliability analysis, layout review, and advanced-node optimization. Collaborates with layout, digital, systems, packaging, and test teams while supporting silicon bring-up and production delivery.

Supports semiconductor fab equipment installation, upgrades, maintenance, troubleshooting, and reliability improvement for RDA and metrology tools. Leads root-cause investigations, preventive maintenance scheduling, equipment performance analysis, project prioritization, capacity planning, vendor coordination, and continuous improvement initiatives. Uses analytics, automation, visualization, and AI to improve uptime, predictive maintenance, reporting, throughput, and equipment health.

Design and validate analog, power, and mixed-signal electronic circuits for semiconductor test systems. Create schematics, collaborate on PCB layouts, run circuit simulations, debug and test PCBs, produce technical documentation, automate workflows with scripts, support prototypes and sustaining engineering, and explore AI/LLM tools to improve design and automation.