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As a Senior Design Verification Engineer, you will develop verification plans, support system co-verification, and improve verification methodologies for HBM DRAM products.

Design and qualify probe cards for Micron's products; lead design reviews, manage supplier relationships, and perform statistical analysis.

The Senior Dry Etch Process Engineer improves semiconductor production by developing processes, managing projects, and collaborating across teams to enhance quality and efficiency.

Design and develop block-level IP layouts for DRAM chips using Cadence Virtuoso. Perform layout verification (DRC/LVS/EM), quality checks, documentation, and post-layout optimization. Lead and mentor team members on sub-block layouts, collaborate with global engineering teams, and manage multiple layout projects to meet on-time delivery and quality targets.

Lead enterprise AI consumption finance: define telemetry, unit-economics, allocation policies, vendor normalization, ROI and benefits realization, credit ledger governance, reporting, and cross-functional FinOps-for-AI governance with Finance, Procurement, and AI Operations.

Lead and build PVD/CVD process engineering teams for high-volume manufacturing: hire and develop engineers, drive yield improvement via data-driven problem solving, implement AI/advanced analytics and automation, manage process qualification and ramp, and promote safety and operational alignment with factory goals.

Lead architecture and delivery of high-performance DRAM circuits and subsystems. Optimize floorplans, routing, power delivery, and timings; perform advanced simulations (FINESIM, HSPICE, Verilog); model parasitics and verify signal/power integrity; drive simulation-to-silicon correlation, layout decisions, tape-out support, and cross-functional technical coordination and reviews.

Lead global facilities capital program cost management, driving forecast accuracy, spend compliance, and capital governance. Build KPIs, dashboards, and AI-enabled analytics to support planning, executive reporting, and risk mitigation while coordinating across sites, planning, procurement, and finance.

Lead development, installation, qualification, and optimization of photolithography track equipment and recipes. Investigate process excursions, fix defects and uniformity issues, coordinate suppliers and cross-functional teams, and drive solutions to improve yield, cost, and throughput for high-volume semiconductor manufacturing.

Lead development and optimization of manufacturing-ready photolithography processes (365/248/193nm immersion), collaborate with suppliers, create design/layout methodologies, apply data analytics and machine learning for root-cause analysis and yield improvement, and document results including IP disclosures.