Top Tech Jobs & Startup Jobs

Own and scale formal verification for complex SoC blocks, including CPUs, floating-point units, vector engines, and datapaths. Develop SVA properties, formal testbenches, constraints, abstractions, equivalence checks, and coverage strategies. Debug counterexamples, close difficult proofs, and build reusable formal applications. Partner with architecture, RTL, and simulation teams while maintaining automation, CI, regressions, and proof tracking. Apply formal methods to arithmetic correctness, protocols, security, low-power, CDC/RDC, and AI hardware verification.

Develop and execute verification strategies for a next-generation Physical AI SoC. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification flows. Verify digital blocks, memory systems, interconnects, processors, DMA engines, and complete HW/SW behavior. Perform performance, latency, QoS, emulation, FPGA prototyping, pre-silicon bring-up, post-silicon debugging, and hardware-software root-cause analysis.

Lead system-level design verification for a next-generation Physical AI SoC from verification planning through sign-off and tape-out. Own verification architecture, coverage goals, regressions, and risk tracking while coordinating boot, security, clock/reset, low-power, IO, and memory subsystem verification. Build and guide a verification team, remain hands-on in SystemVerilog and UVM, and partner with architecture, RTL, firmware, software, CAD, and infrastructure teams on simulation, emulation, and pre-silicon bring-up.

Own front-end semiconductor design and verification automation from RTL entry through DFT and implementation handoff. Responsibilities include RTL build, lint, CDC, formal, register generation, simulation, regressions, coverage, emulation, FPGA prototyping, and AI-assisted tooling. The role also manages EDA tool versions, distributed compute, flow health, maintenance, and collaboration with design, verification, DFT, and physical design teams.

Leads IT infrastructure and operations across hybrid cloud, on-premises, HPC, engineering compute, storage, networking, security, CI/CD, and employee technology. Owns capacity planning, disaster recovery, IAM, endpoint security, compliance readiness, service desk operations, budgets, vendors, and facilities technology. Manages and grows the IT team while supporting semiconductor and AI engineering workloads, protecting design IP, and ensuring infrastructure readiness for tape-outs and product releases.

Design and optimize RTL for key portions of a next-generation Physical AI SoC. Own significant blocks through microarchitectural definition, implementation, optimization, and tapeout while collaborating with architecture, software, verification, and physical design teams. Contribute to compute engines, memory subsystems, interconnects, DMA, control processors, and power-management logic. Analyze performance, power, and area tradeoffs, lead design reviews, debug complex systems, and mentor junior engineers.

Define and build the software architecture underlying Velaura’s Physical AI platform, including SDKs, runtimes, drivers, firmware, compilers, developer tools, and workload orchestration. Lead hardware/software co-design, performance optimization, profiling, and integration with ROS2, DDS, robotics, drones, and autonomous systems. Establish engineering processes and help develop a high-performing platform software team enabling efficient AI deployment across heterogeneous computing systems.

Administer and improve enterprise infrastructure across Linux, Windows, macOS, cloud, virtualization, networking, storage, backup, identity, and endpoints. Develop automation, maintain secure configurations, monitor systems, remediate vulnerabilities, investigate incidents, and support compliance initiatives. Provide Tier 2/3 desktop engineering, device provisioning, onboarding and offboarding, endpoint management, troubleshooting, and documentation. Collaborate with engineering, security, and operations teams to deliver reliable, scalable, and secure infrastructure.

Lead RTL development for a next-generation Physical AI SoC, translating system architectures into production-quality microarchitectures and silicon. Responsibilities include hardware/software co-design, compute and memory subsystem design, interconnect and control logic, performance-power-area optimization, architecture and RTL reviews, cross-functional collaboration, process development, and mentoring RTL engineers. The role requires deep digital design expertise, Verilog/SystemVerilog experience, complex SoC development, and full-cycle ownership through silicon bring-up.

Own the functional safety architecture and lifecycle for Physical AI SoCs, from early architecture through tape-out, qualification, and production. Lead hazard analysis, FMEDA, FTA, fault analysis, safety metrics, and safety mechanisms across compute, AI accelerators, memory, and interconnects. Define hardware/software safety requirements, safety cases, and SEooC assumptions; coordinate certification and audits; establish safety processes; and mentor cross-functional silicon, firmware, software, and product teams.