Top Tech Jobs & Startup Jobs

Design and architect high-speed chip-to-chip and rack-scale interconnects for AI inference infrastructure. Specify fabrics, transport/link protocols, topologies, and optimize bandwidth, latency, power, area, reliability. Collaborate with SoC, package, and software teams and influence industry standards.

Define strategy, roadmap, and execution for next‑generation AI memory products. Drive customer engagements with hyperscalers/chipmakers, translate requirements into MRD/PRD, lead cross‑functional execution (ASIC, firmware, NAND, supply chain), build business cases, and maintain competitive intelligence for AI/high‑performance memory architectures.

Lead enterprise architecture strategy across business and technology domains, modernize application and platform landscapes, establish hybrid/multi-cloud and data/AI platforms, enforce architecture governance, drive API-first/event-driven integration, and translate business strategy into architecture roadmaps to reduce technical debt and enable measurable business outcomes.

Lead global strategic sourcing for semiconductor categories (especially DRAM). Develop and implement commodity strategies, conduct should-cost analysis, negotiate contracts, manage suppliers and performance, monitor market trends, and collaborate cross-functionally to support NPI and procurement objectives.

Serve as finance business partner to Global Procurement, providing financial analysis for sourcing, supplier negotiations, spend management, KPI monitoring, forecasting, and cost optimization to support procurement decisions and drive savings.

Lead design and implementation of SAP S/4HANA RISE Finance solutions. Drive fit-to-standard workshops, define target processes, produce functional designs, oversee configuration, ensure compliance (SOX), coordinate integrations and data migration, support testing and change management, and liaise between business, technical teams, and SI partners for go-live readiness.

Lead architecture of AI/ML accelerator ASICs integrated with AI storage and xPU devices. Define I/O subsystems (UCIe/PCIe/CXL), DMA, memory hierarchies (HBM), NoC, and firmware/software interactions. Author specs, evaluate PPA tradeoffs, collaborate with cross-functional teams, guide pre/post-silicon validation, and optimize systems for large-scale LLM training and inference.

Provide high-level administrative support to senior consumer product leaders: manage complex calendars, coordinate domestic and international travel and visas, organize meetings/offsites, reconcile expenses, prepare and edit presentations, maintain files, and proactively solve operational issues to ensure efficient executive team operations.

Define and author AI/ML accelerator ASIC and AI Storage system architectures (UCIe/PCIe/CXL), specify I/O subsystems and DMA, evaluate PPA tradeoffs, collaborate with RTL/DV/firmware teams, perform LLM workload characterization, and guide pre- and post-silicon validation to optimize performance, power, area, and endurance.

Lead system-level architecture for AI inference and advanced memory solutions, optimize compute/memory bottlenecks, map ML workloads to hardware, drive hardware/software co-design, and provide technical leadership across chiplet, SoC, and memory subsystem designs.