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Define and guide architecture for high-performance ASICs supporting AI accelerators, networking, and data center workloads. Develop architectural and micro-architectural specifications, model performance, optimize power, performance, and area, and lead trade-off studies and design reviews. Collaborate with RTL, verification, physical design, firmware, and software teams while defining power-management strategies and mentoring engineers.

Design and implement production-ready RTL for complex digital subsystems, translating architectural specifications into scalable microarchitectures. Collaborate with architecture, verification, and physical design teams on correctness, synthesis, timing, power, and area closure. Perform linting, CDC analysis, simulation, debug, integration, and design reviews. Contribute to reusable RTL, design methodologies, tooling, and AI-assisted workflows.

Develop and maintain RTL verification environments for ASIC and FPGA designs using UVM and SystemVerilog. Create coverage-driven plans, directed and constrained-random tests, assertions, and reusable verification components. Analyze simulations, debug design issues, track functional and code coverage, automate regressions with Python, and drive verification through closure. Collaborate with RTL engineers on reviews, testability, and reliable silicon delivery while verifying protocols including AXI, APB, PCIe, Ethernet, SPI, and I²C.

Architect and deliver advanced multi-die IC packages for high-performance AI accelerators. Responsibilities include package and substrate design, bump and ball mapping, high-speed signal routing, power distribution, manufacturability, thermal and mechanical optimization, subcontractor management, and collaboration with TSMC or OSAT. The role also supports package bring-up, failure analysis, debugging, qualification, and evaluation of emerging packaging technologies.

Develop and maintain UVM-based RTL verification environments for ASIC DFT logic. Create coverage-driven plans, directed tests, assertions, and automated regressions; verify MBIST, scan, ATPG, JTAG, boundary scan, and other DFT functionality. Debug simulation and design issues, validate gate-level behavior and tester patterns, support SoC-level and post-silicon bring-up, and collaborate with DFT design and manufacturing engineers to deliver reliable silicon.

Own complex ASIC and SoC physical implementation from synthesized netlist through signoff, including floorplanning, placement, CTS, routing, timing closure, ECOs, physical verification, and power integrity. Lead cross-functional timing and implementation convergence, develop automation and methodologies, resolve advanced-node challenges, and provide technical mentorship. Partner with RTL, architecture, DFT, verification, package, and SI/PI teams while driving PPA, runtime, quality, and tapeout readiness.

Build and maintain automated testing frameworks for distributed AI training and inference workloads. Develop end-to-end integration and stress-testing plans, validate GPU and hardware-software interactions, and troubleshoot failures in large-scale distributed clusters. Collaborate with systems engineers using telemetry and profiling tools to identify root causes and performance bottlenecks. The role requires Python automation, test framework development, containerization, and CI/CD experience, with Kubernetes, infrastructure automation, networking, and firmware testing experience preferred.

As a System Software Engineer, you will design communication primitives for AI models, optimize performance for training workloads, and benchmark performance on clusters.

Delos is a stealth-mode startup seeking to build foundational technology for AI data centers, fostering a collaborative and responsible working environment.