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The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

The role involves leading architecture definition for next-gen GPUs, driving performance modeling, integration, and collaboration across multiple teams. Responsibilities include defining microarchitecture, optimizing performance, and supporting silicon bring-up while contributing to product roadmap planning.

Conduct research on high-performance computing algorithms, translate advanced mathematics into discrete computational models, benchmark and analyze competing approaches, provide performance estimations, and collaborate with hardware architects to define proof-of-concept features and system requirements.

The RTL Design Tech Lead will manage RTL design for ASIC/SoC projects, lead a team of engineers, ensure high design quality, and drive projects from architecture to tapeout.

Lead the architecture definition for advanced semiconductor products, focusing on SoC design, performance modeling, and cross-functional collaboration in a tech lead role.