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The Director of System Applications Engineering will lead a team for deploying optical transceivers, oversee technical engagement, and resolve complex system issues, influencing product decisions and managing customer relationships for AI networking platforms.

Lead the development of packaged silicon photonics solutions, translating customer needs into technical requirements, while driving cross-functional execution and validation.

The Senior Technical Program Manager oversees silicon tapeouts, advanced packaging, and system integration, ensuring timely delivery while managing schedules and stakeholder communications.

Design and deliver high-performance analog/mixed-signal circuits, collaborating with various engineering teams for silicon validation and optimization.

Lead end-to-end process design, automation, and continuous improvement across NPI, supply chain, manufacturing, and post-sale support. Drive process discovery, future-state architecture, automation specs, KPI dashboards, governance forums, and change management to improve cycle time, quality, and cost outcomes.

Lead FP&A and revenue management for the US R&D lab, ensuring budget oversight, financial reporting, and strategic planning. Partner with sales and drive automation in finance processes.

Lead supplier strategy and sourcing for silicon photonics, advanced packaging, and optical components. Own supplier selection, negotiations, contracts, cost optimization, risk mitigation, NPI-to-HVM transitions, and supplier performance management. Collaborate with engineering, operations, and finance to align supply with product roadmaps and scale manufacturing.

Build a pre-silicon SystemC/TLM-2.0 virtual platform (ISS-backed MCU, peripherals, UCIe transactor) that runs real firmware. Perform architecture and performance modeling (latency, throughput, buffer sizing), deliver golden reference and behavioral mixed-signal/analog models for DV, and partner with FE architects and firmware leads to align models, RTL, and firmware for early bring-up.

Lead front-end micro-architecture and own the high-speed datapath connecting UCIe to the optical front end. Define RTL coding/CDC standards, timing- and floorplan-aware partitioning, clock/reset and low-power schemes, verification expectations, DFT/debug hooks, and IP integration. Mentor and grow the front-end team and collaborate with backend, DV, and modeling leads to achieve multi-hundred-Gbps physical closure and verifiable architectures.

Lead power integrity architecture and analysis for 2.5D/3D heterogeneous packages integrating electrical and photonic ICs. Perform PDN modeling, simulation, lab validation, component selection, and cross-functional co-design to minimize noise, IR drop, and reliability risks for AI/HPC accelerators through sign-off to production.