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Develops and executes UVM-based functional verification for chiplet blocks and subsystems. Responsibilities include building testbenches, writing constrained-random tests, achieving coverage closure, integrating VIP, debugging regressions, verifying firmware and mixed-signal models, and supporting emulation, FPGA prototyping, gate-level, and low-power verification. The role collaborates with design, architecture, modeling, and DFT teams through signoff.

Develop C#/.NET desktop manufacturing software for optical transceiver testing. Build WPF/MVVM interfaces, concurrent test execution, hardware drivers, instrument resource management, RPC services, and embedded Python testing capabilities. Design reliable, testable systems using clean architecture, MongoDB, GitHub Actions, and automated deployment to Windows machines. Diagnose distributed failures through logs and telemetry while supporting software operating at manufacturing scale.

Leads end-to-end design verification for a photonics chiplet, defining verification strategy, UVM architecture, coverage, signoff, regressions, emulation, FPGA prototyping, UCIe compliance, mixed-signal co-simulation, low-power and gate-level verification. Owns performance validation, firmware and boot-flow verification, and grows a cross-functional DV team across FEC, UCIe, MCU, datapath, and full-chip domains.

Designs high-speed analog and MMIC circuits for photonic interconnects from architecture through tapeout and silicon validation. Responsibilities include schematic design, EM modeling, parasitic extraction, simulation, physical verification, reliability signoff, automation scripting, layout collaboration, and lab characterization. Requires advanced analog IC design expertise, high-frequency analysis, EDA proficiency, and experience with advanced process technologies.

Lead full-custom analog and mixed-signal layout for advanced CMOS silicon platforms, including PLLs, converters, regulators, and high-speed I/O. Define layout methodologies, drive parasitic-aware implementation, own DRC/LVS and physical verification closure, and support tape-out readiness. Collaborate with circuit, physical design, process technology, and design kit teams on floorplanning, PDK qualification, and post-layout analysis. Mentor engineers and coordinate contractors while establishing scalable physical design roadmaps across silicon programs.

Provides first-line T1 and T2 helpdesk support across macOS, Windows, and Linux. Responsibilities include ticket triage, device imaging and deployment, onboarding and offboarding, identity administration, connectivity troubleshooting, hardware asset management, conference room AV support, and maintaining IT documentation. The intern will also collaborate on endpoint management, SaaS administration, identity access management, and security initiatives.

Build and own data pipelines, models, quality checks, dashboards, and visualizations for manufacturing and test data. Partner with optical, manufacturing, and quality engineers to create reliable data solutions, improve pipeline performance and cost, and support engineering and leadership decisions. Establish software engineering practices for data systems, guide technical direction across distributed sites, and mentor other engineers.

Owns strategy and execution for high-speed optical interconnect product lines, including co-packaged optics, 800G, and 1.6T transceiver platforms. Coordinates engineering, manufacturing, suppliers, quality, supply chain, sales, finance, and operations to drive product development, validation, launch readiness, customer adoption, and production transfer. Responsibilities include market and competitive analysis, customer engagement, technical trade-off evaluation, roadmap execution, risk management, business cases, and leadership reporting.

Lead development of packaged silicon photonics and optical interconnect products from requirements through validation and production. Define product requirements, analyze optical links, coordinate engineering and external partners, guide packaging and assembly execution, and establish testing strategies. The role requires hands-on laboratory work, customer and supplier engagement, cross-functional leadership, and attention to manufacturability, reliability, thermal performance, and scale-up readiness.

The Director of Silicon Test Engineering will lead test strategy and execution for silicon photonics products, optimizing test solutions and ensuring product reliability. Responsibilities include managing ATE test development, driving yield optimization, and collaborating with cross-functional teams while building a high-performing engineering team.