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Lead mission-level engineering for national security programs: define and negotiate mission concepts, perform payload-to-bus compatibility and architecture studies, coordinate cross-functional engineering teams, manage customer technical engagements, and produce system-level technical documentation and requirements.

Lead EMI/EMC testing for satellite electronics, define compliance standards, collaborate with engineers to improve designs, and manage test campaigns for certification.

Lead manufacturability and production ramp for large satellite subsystems: define production-ready build flows, tooling, and capacity; lead first-article builds and flight hardware integration; deploy advanced manufacturing and automation; mentor junior engineers; drive DFM and continuous improvement to reduce cost, risk, and cycle time.

The Senior HR Business Partner will shape K2 Space's culture and people strategy, ensuring compliance with labor laws and fostering a positive work environment.

The Senior ASIC Physical Design Engineer will oversee the full physical design flow for complex SoCs, ensuring timing closure and optimization while collaborating with various teams and external providers on satellite projects.

The Senior Satellite Mechanical Engineer will lead the design and analysis of mechanical structures for satellites, collaborating with cross-functional teams, and managing hardware development and testing.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.

Lead DFT architecture and implementation for complex mixed-signal SoCs. Responsible for RTL-level scan and BIST insertion, ATPG flow development and coverage closure, mixed-signal test strategies, DFT verification and signoff, silicon bring-up support, and methodology/automation improvements while collaborating with design, verification, and physical design teams.

Lead development of behavioral models and mixed-signal verification methodology for analog/mixed-signal SoCs. Create Verilog/SystemVerilog/Verilog-AMS models, build co-simulation testbenches, integrate AMS into UVM digital environments, support architectural exploration, and drive cross-functional alignment with RF, analog, and digital teams to ensure successful silicon tapeout and bring-up.

Develop and execute verification plans for block, subsystem, and full-chip designs. Build SystemVerilog/UVM testbenches, write SVA, apply constrained-random and directed tests, run simulations, triage failures, drive root-cause analysis, maintain coverage and regression suites, and collaborate with cross-functional teams through sign-off.