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The Principal Analog Design Engineer will design high-speed analog circuits and collaborate with teams to optimize performance in photonic AI systems.

Design, simulate, and optimize passive silicon photonic components for AI applications, collaborate with foundry partners and cross-functional teams.

Develop hardware-aware post-training quantization and model adaptation methods for LLMs, diffusion models, and other machine learning applications targeting optical inference hardware. The role involves numerical and constrained optimization, controlled experiments, research-quality implementations, model deployment across PyTorch, Triton, and JAX, GEMM optimization, and collaboration with hardware and software teams to co-optimize AI architectures. The engineer will also publish research while protecting company intellectual property.

Lead the architecture, design, simulation, validation, and commercialization of silicon photonic devices (grating couplers, waveguides, SOAs, photodetectors). Develop link budgets, collaborate with foundries using PDKs, perform DFM/DFT, run optical simulations, characterize devices in lab, integrate with electro-mechanical and software teams, lead design reviews, support IP and patent filings, and mentor junior engineers.

Lead full-cycle technical recruiting for hardware, semiconductor, and photonics roles. Source senior and junior candidates, manage interview processes and scheduling, partner with Talent to build hiring workflows, and represent technical credibility to candidates and hiring managers.

Develop and optimize high-performance Analog IPs for photonic AI platform, perform custom IC layout, and coordinate with designers and EDA vendors.

Lead Security Engineer to design and defend cloud, network, and systems infrastructure. Implement zero-trust, IAM/PAM, SIEM/EDR, vulnerability management, incident response, vendor/customer security assessments, and drive SOC 2 Type II compliance while partnering with engineering and legal.

Develop low-level firmware for a hybrid optical-electronic LLM accelerator: implement board/system management, hardware interfaces, debugging/profiling tools, validate performance, collaborate on software-hardware integration, and support customer integration.

Lead end-to-end datacenter scale-out networking architecture for the T100 platform: host networking stack to EIC PCIe bridge, NIC integration, and DMA into HBM. Define RDMA/transport/offload (RoCEv2, UET), PCIe P2P/ACS policies, queue/completion semantics, vendor selection, collective communication modeling, DPU roadmap, standards representation, and mentor architecture and software engineers.

Lead and build Neurophos' in-house IT function across Sunnyvale and Austin. Own on-prem Linux compute for EDA/CAD, storage, backup, SSO/IdP (Okta), GitHub Enterprise, cloud (Azure) administration, network design, MSP governance, endpoint fleet management, and insourcing roadmap. Design hybrid connectivity, security/compliance evidence, and scale infrastructure from ~50 to 150+ employees while hiring and mentoring the IT team.