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The Senior Staff Physical Verification CAD Engineer will develop CAD and EDA tools, collaborate with teams on semiconductor design, optimize design methodologies, and support physical verification processes.

The Senior Staff Design Engineer will design, develop, and debug high-speed digital designs, focusing on IPs for computing and signal processing, requiring extensive experience in RTL design and verification.

The Staff Software Engineer will design, implement, and optimize SSD firmware features, conduct failure analysis, and ensure successful cross-team collaboration for SoC production.

The role involves developing verification strategies for SoCs, leading UVM testbench architecture, and ensuring functional correctness using automation and collaboration with design teams.

Develop and maintain UVM testbenches and verification environments for complex SoC architectures. Create test plans and strategies, implement tests to meet coverage goals, analyze designs, debug failures, and collaborate with designers to resolve issues.

Lead architecture and implementation of SystemVerilog/UVM verification environments for complex SoCs. Define test strategies and testplans, write random and coverage-driven tests, debug failures with designers, drive SoC verification methodology, and provide technical leadership and mentoring across distributed verification teams to ensure pre-silicon correctness and productivity improvements.

Lead and own portions of SoC digital design and integration from floorplan to tape-out. Integrate IP blocks, run static checks, simulations and CDC analysis, assist verification, drive timing closure, develop processor IP micro-architecture, and build automation while leveraging EDA and next-generation AI tools.

Lead NPI test development for Packaged Integrated Voltage Regulators (PIVR/IVR). Develop electrical test plans, ATE hardware (load boards, sockets) and firmware, and drive pre- and post-silicon validation and production test programs while collaborating with cross-functional teams to support HVM ramp.

Design, verify and implement high-performance PHY and DSP ASIC blocks. Develop ASIC specs, architecture and RTL (Verilog/SystemVerilog). Create and execute verification plans, run lint/CDC/power analyses, optimize datapath designs, and collaborate with global teams.

Lead development of ATE test solutions for characterization, wafer sort and production on Advantest 93K and/or Teradyne platforms. Design high-speed ATE hardware, create test plans, convert design test patterns to ATE format, optimize test flows and collaborate with DFx and Design to improve yield and release production test programs.