Top Tech Jobs & Startup Jobs

Supports Kinaxis Demand and Supply Planning platforms, including configuration, forecasting workflows, supply-demand balancing, integrations, troubleshooting, data governance, and process optimization. Partners with planners and IT to gather requirements, document processes, monitor forecast performance, and implement statistical and ML-based planning improvements across global operations.

Lead end-to-end product quality and reliability across the semiconductor product lifecycle. Define and execute Product Quality Plans, lead qualification (DVT/PVT/MP), enforce manufacturing and supplier quality controls, drive failure analysis and CAPA, own PCN/change control, represent quality to executives and customers, and mentor junior PQEs.

Owns enterprise supply planning platforms, primarily Kinaxis RapidResponse/Maestro. Leads solution design across supply, inventory, capacity, fulfillment, and S&OP/IBP; manages Oracle ERP integrations, data models, automation, troubleshooting, governance, and operational support. The role also develops AI-assisted planning tools and automation use cases, partners with global teams and vendors, and translates business requirements into scalable technical solutions.

Lead NPI test engineering strategy and team for advanced multi-site SoCs. Drive ATE test solutions (Advantest 93K/Teradyne UltraFLEX), define DFT/testability, oversee wafer sort, characterization, and production testing, optimize test programs to reduce time and improve yield, coordinate cross-functional issue resolution, resource planning, program reviews, and standardization to accelerate time-to-market.

Develop and optimize semiconductor test programs on the Advantest 93K platform for characterization, production, and wafer sort. Responsibilities include designing tester hardware for high-speed testing, creating test plans, converting simulation patterns to ATE formats, supporting DFT/DFM reviews, improving yield and test time, and releasing production programs. The role requires collaboration with design and product engineering teams, strong problem-solving skills, and software development using C/C++, Perl, Python, and Linux.

Leads Marvell’s global test hardware engineering organization across ATE load boards, probe cards, sockets, and handler change kits. Oversees hardware strategy, design, supplier management, NPI, production support, capacity planning, budgets, and technology qualification. Builds and manages a worldwide team, partners with Test, Product, Design Engineering, and Supply Chain, and drives first-time-right hardware designs through manufacturing ramp. Requires semiconductor test hardware expertise, SI/PI knowledge, thermal and mechanical engineering oversight, and extensive leadership experience.

Develop and optimize semiconductor test programs on the Advantest 93K platform for characterization, production, and wafer sort. Design high-speed tester hardware, create test plans, convert simulation patterns to ATE formats, and improve test yield and test time. Collaborate with design, DFT/DFM, and product engineering teams to ensure testability and production readiness.

Supports digital IC design and implementation for high-performance semiconductor products. Develops and verifies RTL blocks, performs synthesis, static timing and power analysis, debugs designs, explores design methodologies, and collaborates with architecture, verification, and physical design teams. The intern contributes to real chip design efforts involving cloud, AI, storage, networking, and high-speed connectivity applications.

Design and verify high-performance RTL blocks for digital ICs, including synthesis, static timing analysis, timing signoff, power analysis, and debugging. Interns collaborate with architecture, design verification, and physical design teams on ASIC and SoC projects, investigate design methodologies, and contribute to real semiconductor products for cloud, AI, storage, and networking applications.

Lead digital ASIC design for high-performance connectivity silicon supporting AI data centers. Responsibilities include SoC microarchitecture, SystemVerilog RTL development, ASIC front-end flows, timing and power optimization, subsystem integration, verification strategy, emulation, FPGA prototyping, and silicon bring-up. The role focuses on DSP pipelines, high-speed datapaths, Ethernet protocols, PHY logic, and advanced process nodes while mentoring engineers and driving technical direction.