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Lead the design verification team for ASIC development, ensuring high-quality product delivery through effective collaboration and innovative methodologies.

The Staff Hardware Engineer will design, develop, and test electrical hardware for optical modules and AI platforms, collaborating on specifications, performing testing, and supporting production.

Lead development of ATE test solutions for characterization, wafer sort, and production on Advantest 93K/Teradyne UltraFLEX. Design high-speed test hardware, define test methodologies, translate simulation patterns to ATE programs, optimize test flows, and collaborate cross-functionally to improve yield and release production test programs.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest/Teradyne platforms. Design high-speed ATE hardware, define test methodologies, translate simulation patterns to production test programs, optimize test flows, and collaborate with product, hardware, design, and firmware teams to improve yield and test efficiency.

The Principal Hardware Engineer, Optics is responsible for designing, developing, and testing electrical hardware for optical modules and AI platforms, mentoring junior engineers, and collaborating across teams to ensure project success.

The Principal Analog and Mixed-Signal IC Design Engineer will design sophisticated CMOS transceiver products, conduct architectural investigations, perform design verification, and collaborate with digital teams.

Lead end-to-end NPI supply planning for semiconductor programs from prototype through high-volume production. Own part setup and BOM execution in Oracle, manage WIP and supplier execution, align supply plans with PMO and Engineering, present risks and status to senior leadership, and drive data integrity and process improvements to ensure on-time ramps and inventory readiness.

Develop and maintain UVM/SystemVerilog SoC-level verification environments, create test plans and tests to meet coverage goals, debug failures with designers, and mentor junior engineers. Work involves verification tool usage, regression setup, and scripting for automation.

Lead end-to-end verification of PCIe/CXL subsystems: define verification plans, build scalable UVM/SystemVerilog testbenches, integrate VIPs, create constrained-random and directed tests, implement SVA, drive coverage closure, debug protocol and coherency issues, measure performance, automate regressions, and collaborate with design, firmware, and validation teams while mentoring junior engineers.

Support and maintain analog/mixed-signal (AMS) simulation environments for FinFET and BiCMOS high-speed designs. Collaborate with analog designers, EDA vendors, TCAD and foundry teams to debug device/circuit modeling issues, evaluate AMS tools, define custom circuit checks and model QA flows, and create automation scripts to improve verification efficiency.