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Reposted 7 Days AgoSaved
In-Office
Boise, ID, USA
27-53
Internship
27-53
Internship
Semiconductor
The Design Verification Intern will verify SOCs, writing and executing verification plans, developing tests, and debugging failures using EDA tools.
Top Skills: Eda Verification ToolsLinuxPerlPythonSystem VerilogUvm
8 Days AgoSaved
In-Office
Santa Clara, CA, USA
120K-180K
Senior level
120K-180K
Senior level
Semiconductor
The role involves improving demand forecast accuracy, implementing ML models, and collaborating with various teams to analyze market trends.
Top Skills: Machine LearningExcelMS OfficePower BI
8 Days AgoSaved
In-Office
2 Locations
67K-101K
Mid level
67K-101K
Mid level
Semiconductor
The Travel & Credit Card Program Specialist manages all aspects of corporate travel, supports employees with travel issues, oversees the credit card program, and collaborates with multiple departments for a seamless experience.
Top Skills: American ExpressConcurMS Office
8 Days AgoSaved
In-Office
Westborough, MA, USA
31-61
Internship
31-61
Internship
Semiconductor
As an RTL Design Intern, you'll integrate SoCs for cloud and AI processors, verify designs, and assist in debugging verification tests.
Top Skills: CPerlPythonVerilogVhdl
8 Days AgoSaved
In-Office
Irvine, CA, USA
31-61
Internship
31-61
Internship
Semiconductor
The intern will design, simulate, and verify analog blocks for optical transceivers, test existing designs, and collaborate on implementations.
Top Skills: CadenceMatlabPython
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8 Days AgoSaved
In-Office
Santa Clara, CA, USA
31-61
Internship
31-61
Internship
Semiconductor
Design and verify high performance analog and mixed signal circuits for CMOS transceivers, focusing on ADC based applications using various simulation tools. Work involves layout guidance and testing in a lab environment.
Top Skills: CadenceCmos TechnologiesHsimHspiceMatlabSpectreSpiceVerilog
Reposted 8 Days AgoSaved
In-Office
Santa Clara, CA, USA
224K-336K
Expert/Leader
224K-336K
Expert/Leader
Semiconductor
The Senior Distinguished Engineer will lead architectural design for networking ASICs, focusing on performance, collaborating with teams, and mentoring others.
Top Skills: Advanced Packaging TechniquesAsic DesignChiplet ArchitecturesMulti-Die SystemsSemiconductor ProcessesSerdes
Reposted 8 Days AgoSaved
In-Office
Santa Clara, CA, USA
140K-210K
Senior level
140K-210K
Senior level
Semiconductor
Lead high-speed and high-performance SerDes development, support IP characterization, collaborate with design teams and provide instructions to layout engineers.
Top Skills: Analog Ic DesignHigh-Speed InterconnectPam4SerdesTsmc Process
Reposted 8 Days AgoSaved
In-Office
Santa Clara, CA, USA
16-32
Internship
16-32
Internship
Semiconductor
The intern will develop logistics dashboards using Power BI, support project implementation, and identify workflow improvements for cost savings and efficiency.
Top Skills: ExcelPower BI
Reposted 8 Days AgoSaved
In-Office
Santa Clara, CA, USA
18-36
Internship
18-36
Internship
Semiconductor
The intern will design and maintain dashboards, perform data analysis, monitor supply chain metrics, and collaborate with various stakeholders for improvements.
Top Skills: DaxPower BIPythonQlikviewRSQLTableau
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