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Lead verification architecture, execution, emulation and post-silicon validation for next-generation ASICs. Drive verification methodologies, lab bring-up, emulation toward successful tapeout, and lead cross-functional ASIC development teams.

Lead verification architecture, execution, and delivery for next-generation ASICs. Drive emulation, post-silicon validation, lab bring-up, and PSV. Guide verification methodologies, tools, and front-end ASIC processes. Collaborate cross-functionally, lead teams, and ensure successful tapeout and high-quality ASIC products.

Lead verification of complex SoC/IP designs using UVM and SystemVerilog, define verification strategy and test plans, drive RTL simulation, emulation, and post-silicon validation, perform deep root-cause analysis, apply formal verification (SVA/properties), mentor engineers, improve automation and regression infrastructure, and influence architecture and design-for-verification decisions to achieve sign-off.

Lead architecture definition, performance modeling, micro‑architecture and RTL development, and HW/SW co-design for CXL SoC products. Drive cross-functional teams from architecture through tape-out and post‑silicon, interact with customers, and improve productivity for next‑generation datacenter IP/SoC designs.

Lead SoC digital design and integration efforts including RTL design in SystemVerilog, floorplanning, IP interconnection, CDC and timing closure, static checks, and post-silicon debug. Drive processor IP micro-architecture and collaborate with verification, physical design, DFT, and packaging teams. Use EDA tools, simulations, scripting (Python/Tcl), automation, and AI-enabled workflows to deliver tape-out quality silicon.

Lead development and automation of physical verification CAD/EDA flows (DRC/LVS) and runsets using Calibre and ICV. Integrate and maintain EDA toolchains, support tape-outs and foundry interfaces, debug verification issues, create validation tests and documentation, and provide technical guidance and training across design teams.

Lead board-level architecture, schematic/BOM creation, PCB layout oversight, and manufacturing for photonic/data-center platforms. Drive system bring-up, debugging, validation, cross-functional coordination, vendor management, and project execution to deliver server and rack-level solutions.

As a Test Hardware Engineer, you'll test semiconductor chips, work with design teams to ensure testability, and develop testing strategies as needed.

The Director will define application roadmaps for Legal, Compliance, and Facilities technology, lead implementation of key applications, and manage cross-functional project teams while ensuring stakeholder engagement and operational excellence.

The IP Program Manager manages IP development and delivery for Marvell’s products, collaborating across teams to meet specifications and support engineering management processes.