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The Senior Staff Design Engineer will lead PCIE/CXL subsystem design, define micro-architecture, implement RTL, and support silicon validation, while mentoring junior designers.

Lead the design and delivery of PCIe and memory subsystems, managing teams and ensuring high-quality execution in silicon design.

The role involves defining and implementing PCIE/CXL subsystems, collaborating with various teams, ensuring design quality, and mentoring junior engineers.

The role involves developing verification plans for high-speed memory interfaces, building verification environments, and collaborating with design teams for compliance and coverage closure in ASIC/SoC projects.

Design, verify, and deliver memory subsystem IP for custom chips. Develop verification plans and environments, analyze simulation failures, and contribute to coverage-driven verification efforts.

The role involves designing and verifying high-speed memory interfaces, developing verification plans and UVM environments, performing protocol-level verification, and collaborating with cross-functional teams to ensure compliance and performance.

The role includes verifying PCIe/CXL subsystems, developing testbenches using UVM/System Verilog, and collaborating with multiple teams to ensure quality and compliance.

The Engineering Program Manager drives programs from product definition to deployment, managing execution, schedules, and team alignment to meet business goals and ensure customer satisfaction.

The role focuses on ensuring product integrity through reliability testing, data analysis, and development of qualification plans in semiconductor engineering.

The engineer will develop advanced microelectronic packages, focusing on electrical design, modeling, and characterization for high-speed interfaces, collaborating with various teams to ensure manufacturability and compliance.