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Reposted 3 Days AgoSaved
In-Office
Santa Clara, CA, USA
159K-238K Annually
Senior level
159K-238K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The Principal Engineer will architect simulation test benches, develop and execute test plans, debug failures, and mentor junior engineers in verifying chip designs.
Top Skills: C/C++System VerilogUvm
Reposted 3 Days AgoSaved
In-Office
Santa Clara, CA, USA
175K-261K Annually
Senior level
175K-261K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Design high-performance analog circuits including PLL and SerDes blocks, lead projects, verify systems, and manage documentation and communication within the team.
Top Skills: AdeAnalog Circuit DesignDigital Signal ProcessingSpectreVirtuoso
Reposted 3 Days AgoSaved
In-Office
Santa Clara, CA, USA
173K-260K Annually
Senior level
173K-260K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The Director of Product Marketing will define and drive Cloud and AI fabric solutions, leading product strategy, market requirements, and customer engagement activities to influence next-gen AI infrastructure.
Top Skills: Ai Fabric ArchitecturesEthernet SwitchingPcieUalinkUec
Reposted 3 Days AgoSaved
In-Office
Hudson Valley Mobile Home Park, Town of Newburgh, NY, USA
126K-186K Annually
Senior level
126K-186K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The role involves planning, designing, and verifying digital circuits in SerDes IP, coordinating with cross-functional teams to deliver high-speed communication solutions.
Top Skills: PerlTclVerilog
Reposted 3 Days AgoSaved
In-Office
2 Locations
184K-273K Annually
Expert/Leader
184K-273K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
Lead implementation of DFT/Test for complex ASIC/SoC and chiplet designs using Tessent and related EDA tools. Define DFT architecture, run insertion flows, generate patterns, support STA constraints, and drive post-silicon bring-up and debug. Mentor a small DFT team and enhance methodologies and tools across multi-die custom compute designs.
Top Skills: 2.5D3D IcC-ShellChiplet DftDesign Compiler (Dc)GenusIclIeee 1687Ip-DfxMbistModusNc-SimPdlPerlPost-Silicon Bring-UpPtapPythonScanSpyglassStaStapTclTessentTessent SsnTmax
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Reposted 3 Days AgoSaved
In-Office
Santa Clara, CA, USA
143K-215K Annually
Senior level
143K-215K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The Principal Hardware Engineer will design, develop, and test electrical hardware for optical modules, mentor junior engineers, and collaborate with teams for hardware specifications while ensuring effective troubleshooting and validation of components.
Top Skills: AllegroCad ToolsElectrical Hardware DesignFirmwareOrcadPcb LayoutSemiconductor Processing
Reposted 3 Days AgoSaved
In-Office
San Diego, CA, USA
227K-336K Annually
Senior level
227K-336K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Lead the Design Verification Team at Marvell, managing verification processes, defining methodologies, and ensuring high-quality ASICs while building a strong engineering team.
Top Skills: Asic DevelopmentSoc ArchitectureVerification Methodologies
Reposted 3 Days AgoSaved
In-Office
Santa Clara, CA, USA
224K-336K Annually
Expert/Leader
224K-336K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
As a Senior Distinguished Engineer, lead the architecture of high-performance networking ASICs, foster innovation, and mentor engineers. Collaborate with cross-functional teams to enhance scalable data infrastructures for AI and cloud applications.
Top Skills: Asic ArchitectureChiplet MethodologiesCommunication ProtocolsHigh-Performance NetworkingSilicon DesignSystem-Level Architecture
Reposted 3 Days AgoSaved
In-Office
Westlake Village, CA, USA
120K-178K Annually
Mid level
120K-178K Annually
Mid level
Artificial Intelligence • Automotive • Semiconductor
The role involves the design and validation of high-speed analog circuits, particularly transimpedance amplifiers for optical data communication. Responsibilities include active circuit design, working on millimeter wave structures, and collaborating on post-silicon validation and production transition.
Top Skills: Eda Cad ToolsFinfet CmosSige Bicmos
Reposted 3 Days AgoSaved
In-Office
Santa Clara, CA, USA
148K-221K Annually
Senior level
148K-221K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Design high-speed, low-power analog mixed-signal circuits for SerDes and wireline applications in advanced CMOS. Develop blocks (clock generation/distribution, DLLs, ADCs/DACs, CTLE, VGA, TX drivers, regulators), supervise layout, perform post-silicon validation and lab characterization, use EDA tools, collaborate cross-functionally, and prepare documentation and design reviews.
Top Skills: AdcAdvanced CmosCadenceClock DistributionClock GenerationCtleDacDllsMentor GraphicsSerdesSynopsysTx DriversVgaVoltage Regulators
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