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Design and implement emulation verification environments and reference models for multi-core SoCs. Develop and execute verification test plans, build and bring up emulation models on platforms like Veloce/ZeBu/Palladium, debug firmware and failures, and create tools and scripts to automate verification and regression testing. Collaborate with designers to meet coverage goals and streamline firmware bring-up.

Lead reliability engineering for 2.5D/3D advanced semiconductor packages: perform physics-of-failure modeling, define and execute stress tests, manage OSAT qualifications, select and qualify materials, perform failure analysis (FIB/SEM/TEM/X-ray), drive root-cause and corrective actions, and collaborate with design, process, and suppliers to improve package reliability and manufacturability.

The Principal Engineer will architect and implement DFT/Test on complex IP and SoC designs, lead a team, and innovate DFT methodologies.

The Distinguished Engineer will define architectures for next-gen AI networking switch ASICs, evaluate performance trade-offs, and lead standards development in networking semiconductor architectures.

Lead a team of firmware engineers for CXL and PCIe End Point device development. Responsible for planning, execution, and delivery of software, collaborating across cross-functional groups, and mentoring team members.

Design micro-architecture for chips, implement low-power RTL, collaborate on verification and physical design, and support silicon bring-up.

Design and verify analog circuits through Verilog/SystemVerilog modeling, support model users, and conduct AMS simulations for functionality verification.

Lead the strategy and transformation of FP&A systems at Marvell, focusing on AI integration, modernization of technology stacks, and driving business-critical initiatives.

The Senior Director of Product Line Management will drive product strategy and design wins for silicon photonics solutions, collaborating across teams to ensure market success.

The role involves defining and developing link layer architectures for high-speed interconnects, driving technical decisions, collaborating with cross-functional teams, and mentoring engineers.