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Reposted 22 Days AgoSaved
In-Office
Santa Clara, CA, USA
164K-246K Annually
Senior level
164K-246K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Lead the design and execution of advanced semiconductor solutions, managing program ownership and cross-team collaboration while communicating with stakeholders.
Top Skills: Computer ScienceDigital DesignElectrical EngineeringSemiconductor Industry
Reposted 22 Days AgoSaved
In-Office
Irvine, CA, USA
127K-187K Annually
Mid level
127K-187K Annually
Mid level
Artificial Intelligence • Automotive • Semiconductor
Design and verify high-speed and optical transceivers, focusing on Analog/Mixed-Signal ICs, including performance tests and innovative solutions.
Top Skills: Analog Ic DesignCmosMatlabSpectreSpiceVerilog
Reposted 22 Days AgoSaved
In-Office
3 Locations
168K-249K Annually
Expert/Leader
168K-249K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
The role involves developing advanced packaging technologies, defining architectures, leading co-design efforts, and ensuring product manufacturability and reliability for high-performance computing and AI solutions.
Top Skills: Ansys HfssAnsys SiwaveCadence ApdCadence ClarityCadence Sigrity Powersi
Reposted 22 Days AgoSaved
In-Office
Santa Clara, CA, USA
159K-238K Annually
Expert/Leader
159K-238K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
The Principal Design Verification Engineer will develop verification architectures, write test plans, debug designs, and create scalable software tools for SoC verification. Requires extensive experience in verification methodologies and testbench development.
Top Skills: C/C++System VerilogUvm
23 Days AgoSaved
In-Office
Santa Clara, CA, USA
151K-226K Annually
Expert/Leader
151K-226K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
Lead SI/PI analysis and validation across silicon, package, PCB, and system levels. Perform pre/post-layout SI simulations, PDN design and transient PI analysis, lab correlation and debug, define sign-off criteria, mentor engineers, and resolve cross-domain SI/PI/timing/EMI issues for high‑speed interfaces and products.
Top Skills: Ansys HfssAnsys SiwaveCadence Sigrity (PowersiDdr4Ddr5Equivalent Extraction/Em Simulation ToolsEthernet NrzEthernet Pam4HbmKeysight AdsKeysight EmproLpddrOptimizepi)OscilloscopePcie Gen4Pcie Gen5Pcie Gen6Serdes LinksSiemens HyperlynxSystemsiTdrVna
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Reposted 23 Days AgoSaved
In-Office
Austin, TX, USA
143K-211K Annually
Senior level
143K-211K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The engineer will develop advanced microelectronic packages, focusing on electrical design, modeling, and characterization for high-speed interfaces, collaborating with various teams to ensure manufacturability and compliance.
Top Skills: AdsAnsys HfssCadence ClarityHspiceMatlabPowersiPythonSi-WaveSiwaveSpectre
Reposted 23 Days AgoSaved
In-Office
Irvine, CA, USA
136K-201K Annually
Senior level
136K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The Senior Staff Design Engineer will lead PCIE/CXL subsystem design, define micro-architecture, implement RTL, and support silicon validation, while mentoring junior designers.
Top Skills: AceAmbaArmAxi-4CadenceChiCxlGitMentor/SiemensPciePerlPythonSvnSynopsysSystem VerilogTclVerilog
Reposted 23 Days AgoSaved
In-Office
Irvine, CA, USA
160K-237K Annually
Mid level
160K-237K Annually
Mid level
Artificial Intelligence • Automotive • Semiconductor
The Engineering Program Manager drives programs from product definition to deployment, managing execution, schedules, and team alignment to meet business goals and ensure customer satisfaction.
Top Skills: Ip DevelopmentSilicon Product Development
Reposted 23 Days AgoSaved
In-Office
Santa Clara, CA, USA
134K-201K Annually
Senior level
134K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Design, verify, and deliver memory subsystem IP for custom chips. Develop verification plans and environments, analyze simulation failures, and contribute to coverage-driven verification efforts.
Top Skills: DdrHbmLpddrPerlPythonShellSystem VerilogUvm
Reposted 23 Days AgoSaved
In-Office
Santa Clara, CA, USA
134K-201K Annually
Senior level
134K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The role involves designing and verifying high-speed memory interfaces, developing verification plans and UVM environments, performing protocol-level verification, and collaborating with cross-functional teams to ensure compliance and performance.
Top Skills: Coverage ToolsDdr4Ddr5Emulation PlatformsHbm2Hbm3Lpddr4Lpddr5PerlPythonShellSimulation ToolsSystem VerilogUvmWaveform Debugging Tools
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