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Design and develop high-speed IC packages focusing on signal and power integrity. Perform electrical design, 2D/3D EM modeling, measurements (VNA/TDR), and package/PCB characterization. Interface with suppliers, IC designers, and cross-functional teams to ensure manufacturability, reliability, and cost targets. Automate SI/PI workflows and contribute to new package technology development.

Lead the development and verification of SoC emulation models, optimize performance, automate flows, and collaborate with design teams.

We are seeking a Timing/STA Engineer with expertise in timing constraints development and STA methodologies for intricate SoC designs. Responsibilities include developing timing constraints, conducting static timing analysis, automating STA processes, and collaborating with cross-functional teams for design optimization.

The Director of Application Engineering will lead a team focusing on high-speed SerDes IP, overseeing support, technical leadership, and cross-functional collaboration to ensure optimal deployment and performance across business units and customer projects.

Lead FP&A for the Data Center Switch business unit: budgeting, forecasting, variance analysis, product P&Ls, margin and opex analysis, cross-functional partnering, executive reporting, annual/quarterly planning, strategic initiatives (M&A, ROI, long-range planning), and manage and mentor an FP&A team.

The role involves improving demand forecast accuracy, implementing ML models, and collaborating with various teams to analyze market trends.

The role involves leading SerDes IP integration, coordinating engineering resources, diagnosing signal integrity issues, and supporting high-speed interface applications, while managing customer technical escalations and providing documentation and presentations.

Lead advanced packaging technology roadmap and development for high-performance AI/HPC and networking products. Define package architecture, chiplet topology, PDN and thermal strategies; run signal/power integrity and EM simulations; partner with silicon teams, OSATs and foundries; drive manufacturability, qualification, and volume readiness while creating IP and proof-of-concept technologies.

The Engineering Program Manager leads end-to-end execution of custom semiconductor solutions, managing the program lifecycle, ensuring successful delivery, and collaborating with customers and internal teams.

The Staff Engineer for Lab Operations will oversee all aspects of the Santa Clara hardware lab, including equipment management, vendor relationships, lab organization, and logistics for customer demos and tradeshows.