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Design, simulate, verify, and bring up analog and mixed-signal circuit blocks across the full design flow. Work on production IP including SerDes, Silicon Photonics, ADC/DAC, PLL, clock, LDO, and precision analog circuits in advanced CMOS processes. Collaborate with layout engineers, participate in design reviews, present research and design results, and complete a structured analog design curriculum.

Intern will perform synthesis, floorplanning, place and route, clock insertion, timing analysis, and timing closure for complex ASIC and processor logic blocks. Responsibilities include scripting in Python, TCL, Perl, and Shell; debugging design violations with EDA tools; and collaborating with RTL, synthesis, and design teams to resolve congestion and timing bottlenecks. The role supports designs meeting performance, power, and area requirements.

Design verification intern supporting semiconductor processor and ASIC verification. Responsibilities include developing simulation environments, creating automated tests, debugging hardware and software interactions, analyzing coverage metrics, troubleshooting failures, and collaborating with architects and designers. The role involves pre-silicon emulation, UVM testbench development, RTL integration, and verification of block, cluster, and full-chip designs.

Support physical design of ASIC and processor logic blocks through synthesis, floorplanning, place and route, clock insertion, timing analysis, and timing closure. Write scripts in Python, TCL, Perl, and Shell, use industry-standard EDA tools, debug design violations, and collaborate with RTL, synthesis, and design teams to resolve congestion and timing issues.

Design-for-Test intern supporting DFT design and implementation for system-on-chip products. Responsibilities include learning and running CAD flows, developing SOC designs using Linux and scripting languages, analyzing and debugging DFT features, improving design flows with global CAD teams, and assisting verification using ICL, PDL, SystemVerilog, and UVM.

Supports Marvell Optical PAM4 DSP products, owns customer technical issues through resolution, interfaces with customers and internal engineering teams, and communicates customer needs to marketing and engineering. The intern will apply C and Python skills while developing practical experience with digital signal processing, analog circuits, system hardware, and laboratory problem-solving in optical interconnects for AI and data center applications.

Leads global engineering applications and lab operations, defining modernization, cloud migration, integrated development platform, and Labs-as-a-Service strategies. Oversees engineering toolchains, lab provisioning, security, network architecture, governance, automation, resiliency, observability, and compliance. Partners with Engineering, IT, Security, and Facilities to standardize workflows, protect intellectual property, improve developer productivity, and enable scalable collaboration across global teams.

Responsible for defining and implementing IT PMO strategy, managing project portfolios, overseeing program execution, and optimizing financial resources while ensuring stakeholder alignment and compliance with governance frameworks.

The Principal Test Engineer will lead development of ATE test solutions, innovate high-speed testing hardware, craft test plans, and optimize test flows while collaborating with cross-functional teams.

Support Marvell's global export compliance program with product, software, and technology classification under U.S. and international export and customs regulations. Manage visitor and deemed export processes, support trade due diligence, maintain SOPs and training, prepare classification requests and license applications, and collaborate with engineering, operations, and global teams on compliance projects.