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Reposted 7 Days AgoSaved
In-Office
Santa Clara, CA, USA
94K-141K Annually
Junior
94K-141K Annually
Junior
Artificial Intelligence • Automotive • Semiconductor
The Firmware Engineer conducts PCIe post-silicon bring up and function validations, and implements automation scripts for testing. Requires knowledge in C/C++, Python, and system protocols.
Top Skills: CC++LinuxPciePythonWindows
Reposted 7 Days AgoSaved
In-Office
Santa Clara, CA, USA
141K-211K Annually
Senior level
141K-211K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
This role involves developing semiconductor solutions with a focus on signal and power integrity, impacting data infrastructure across multiple architectures.
Top Skills: Ai ArchitectureCloud ArchitectureData InfrastructureEnterprise ArchitecturePower IntegritySemiconductor SolutionsSignal Integrity
Reposted 7 Days AgoSaved
In-Office
Santa Clara, CA, USA
87K-131K Annually
Junior
87K-131K Annually
Junior
Artificial Intelligence • Automotive • Semiconductor
Support Marvell's Optical PAM4 DSP products, resolve technical issues for customers, and collaborate with engineers and marketing on customer needs.
Top Skills: CPython
Reposted 7 Days AgoSaved
In-Office
Santa Clara, CA, USA
147K-220K Annually
Expert/Leader
147K-220K Annually
Expert/Leader
Artificial Intelligence • Automotive • Semiconductor
Lead a team of firmware engineers for CXL and PCIe End Point device development. Responsible for planning, execution, and delivery of software, collaborating across cross-functional groups, and mentoring team members.
Top Skills: Arm Cortex-AArm Cortex-MCI2CI3CPcieRisc-VSpiUartUsbZephyr
Reposted 7 Days AgoSaved
In-Office
Westlake Village, CA, USA
142K-210K Annually
Senior level
142K-210K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Design and validate FET and BiCMOS circuits for high-speed broadband integrated circuits, including analog and mixed-signal circuits. Collaborate across teams for validation and production.
Top Skills: CmosEda Cad ToolsSige Bicmos
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Reposted 7 Days AgoSaved
In-Office
Burlington, VT, USA
136K-201K Annually
Senior level
136K-201K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Develop SRAM memory solutions and design kits while collaborating with circuit designers to meet market needs in semiconductor IP.
Top Skills: BashClojureEdaGitGitJavaLinuxPerlPython
Reposted 7 Days AgoSaved
In-Office
Santa Clara, CA, USA
159K-238K Annually
Senior level
159K-238K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The Principal Verification Engineer will develop test benches, execute test-plans, debug simulations, and mentor junior engineers in the verification of SoCs for AI and cloud data center applications.
Top Skills: C/C++DpiSystem VerilogUvm
Reposted 7 Days AgoSaved
In-Office
Santa Clara, CA, USA
169K-253K Annually
Senior level
169K-253K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
As a Senior Principal Digital IC Design Engineer, you will develop ASICs, ensure design quality, and mentor junior engineers. Lead RTL development and collaborate on verification activities.
Top Skills: Cdc)Design CompilerEsun)I2CI3CMdioPciePhy/Mac Layer Communication Protocols (EthernetPrimetimeRtl DesignSmbusSpiSueSynthesisTiming ClosureUa LinkUnix-Based Eda Tools (VcsVerification
Reposted 7 Days AgoSaved
In-Office
Santa Clara, CA, USA
157K-235K Annually
Senior level
157K-235K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
The Senior Staff Physical Design Manager will lead physical design projects, mentor team members, oversee resources, and collaborate with ASIC teams to ensure successful design tape-outs. Requires ASIC or SOC experience and technical leadership.
Top Skills: AsicClock Tree SynthesisCmosFloor PlanningGdsNetlistPhysical DesignPhysical VerificationPlace And RouteSocTiming Closure
Reposted 7 Days AgoSaved
In-Office
Santa Clara, CA, USA
159K-235K Annually
Senior level
159K-235K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
Drive yield improvement and process optimization for advanced packaging by building scalable data pipelines, integrating ATE/DFT/fab data, performing statistical and ML-based yield analytics, enabling self-serve analytics, and delivering reports and recommendations across cross-functional teams and external partners.
Top Skills: 2.5D Integration3D IntegrationAutomated Test Equipment (Ate)Cloud AnalyticsCo-Packaged OpticsData WarehousingDesign For Test (Dft)Fan-Out PackagingJmpMachine LearningPythonSQL
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