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Develop embedded firmware for CXL and PCIe endpoint devices, including near-memory accelerators and memory-expansion controllers. Responsibilities include contributing to project goals and schedules, leading distributed engineering projects, collaborating with architecture, QA, validation, systems, product, documentation, and customer teams, and mentoring engineers. The role requires expertise in Zephyr, C/C++, ARM M7 debugging, encryption standards, and PCIe concepts.

Leads a firmware engineering team developing CXL and PCIe endpoint devices. Plans and delivers embedded software, manages engineering resources, coordinates distributed cross-functional teams, mentors engineers, and supports recruitment and talent development. The role requires expertise in C, embedded systems, RTOS environments, Arm and RISC-V architectures, peripheral drivers, secure firmware, TrustZone, secure boot, and embedded debugging. A master’s degree and 12+ years of semiconductor experience are required.

The Sr. Staff Thermo-Mechanical Engineer will focus on mechanical simulation and structural reliability of semiconductor test infrastructure, ensuring mechanical robustness and reliability of high-power semiconductor programs.

Ph.D. interns apply machine learning and AI to semiconductor chip design or enterprise engineering tools. Responsibilities include developing ML models for EDA automation, placement, timing, power, and verification, or deploying LLM, RAG, and agentic systems. Interns will train, evaluate, and deploy models, conduct rigorous experiments, collaborate with engineering and technology stakeholders, assess production performance and safety, and present findings to leadership. The role requires doctoral research in AI, machine learning, computer science, electrical engineering, data science, or a related field.

Ph.D. interns design, simulate, characterize, and validate silicon photonics components, optical engines, and DSP algorithms for PAM4 and coherent optical transceivers. Responsibilities include optical system modeling, link budget analysis, lab testing, silicon bring-up, and collaboration with analog IC, packaging, and systems engineering teams. Interns present research findings and design results while contributing to production-scale optical communications solutions.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K/Teradyne. Design high-speed ATE hardware, create test plans, convert design test patterns to ATE format, optimize test flows, collaborate with DFx/design, and ensure DFT/MBIST and high-speed interface compliance.

Lead development of ATE test solutions for characterization, wafer sort, and production on Advantest 93K/Teradyne UltraFLEX. Design high-speed test hardware, define test methodologies, translate simulation patterns to ATE programs, optimize test flows, and collaborate cross-functionally to improve yield and release production test programs.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest/Teradyne platforms. Design high-speed ATE hardware, define test methodologies, translate simulation patterns to production test programs, optimize test flows, and collaborate with product, hardware, design, and firmware teams to improve yield and test efficiency.

Supports semiconductor process development for 2.5D/3D chip-on-wafer assembly and co-packaged optics. Tracks and analyzes packaging-build data, identifies NPI risks, documents mitigation plans, and summarizes technical progress. Collaborates with foundry and OSAT partners on manufacturing readiness, reliability, design-for-manufacturing, and cost tradeoffs.

Design Verification Interns will develop simulation environments, automated tests, and testbenches for semiconductor processors and SoCs. Responsibilities include analyzing coverage metrics, debugging failed simulations and hardware/software interactions, verifying RTL integration, and collaborating with architects and designers. The role provides hands-on experience with pre-silicon verification, UVM methodology, and industry-standard EDA tools across cloud, AI, storage, and networking chip designs.