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Develop and draw analog/mixed-signal layouts for high-speed SerDes and other AMS IP in FinFET/deep-submicron processes. Collaborate with circuit designers and PV teams to resolve DRC/LVS/ANT/ERC/EMIR issues, using Cadence Virtuoso, Synopsys Custom Compiler, and Mentor Calibre. Provide feedback on schematics, support lab validation, and work across teams to achieve production-ready SoC layouts.

Develop and execute mixed-signal verification plans and testbenches for broadband amplifiers and drivers. Write and run test cases, analyze results, document findings, and collaborate with design and layout teams to resolve issues across SiGe BiCMOS and CMOS process nodes using EDA tools, Python, and hardware description languages.

Lead micro‑architecture and RTL development for high‑performance connectivity ASICs. Define SoC specs, implement SystemVerilog RTL, drive front‑end flows (lint/CDC/synthesis/STA), support timing closure and PNR, collaborate on verification, pre‑ and post‑silicon validation, and mentor cross‑functional teams to deliver tape‑out ready designs.

The role involves leading a layout design team, managing schedules and risks, performing macro-level layout work, and ensuring project tasks are prioritized effectively. Requires deep technical knowledge in analog layout design and hands-on management experience.

The role involves leading the design of custom silicon, shaping micro-architecture, collaborating on verification, and managing cross-team interactions, while building a new team.

The role involves designing, implementing, and verifying micro-architecture and RTL for power management integrated circuits, collaborating with colleagues and customers throughout the design process.

As a Sr Staff SoC Verification Engineer, you will create functional verification environments, write verification test plans, develop tests for multi-core SoCs, and participate in problem-solving activities.

Manage the design verification team for semiconductor solutions, define methodologies and strategies, drive execution, and ensure product quality in a fast-paced environment.

The Senior Staff Applications Engineer will focus on SerDes IP design, providing customer support, optimizing design performance, problem solving and cross-functional collaboration.

Lead and define the DV strategy and methodology for semiconductor verification, managing timelines and building a high-performance engineering team.