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Lead STA signoff processes for complex ASIC designs, defining methodologies and collaborating with design teams to ensure timing closure and optimal performance.

As a Principal Physical Design Engineer, you will lead ASIC development from RTL to GDSII, oversee design flow optimization, and ensure the delivery of high-performance products.

The role involves leading the physical design of ASICs, overseeing all phases from RTL to GDSII, and enhancing design methodologies.

As a Verification Engineer, you will lead the verification of Serdes by developing AMS SystemVerilog models, collaborating with the design team, and ensuring model quality.

As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.

Lead ASIC and platform development, manage cross-functional teams, oversee project timelines, budgets, and vendor relationships to ensure successful program delivery.

The Staff DFT Engineer will define and implement DFT strategies and methodologies, work with cross-functional teams, and support device bring-up for high-volume manufacturing.

As a Staff Digital Verification Engineer, develop verification plans, maintain test environments, and ensure compliance with Ethernet standards while leading junior engineers.

The Senior Staff Physical Verification Engineer leads all physical verification activities including DRC, LVS, and DFM for advanced chip designs, ensuring compliance across multiple foundries and technologies.

Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.