DFT Implementation Lead

Key Responsibilities

• Develop and implement innovative DFT IP and features to support ATE, in-system test, debug, and diagnostics.
• Contribute to flow and methodology development working closely with the digital, analog and physical design teams. 
• Collaborate with cross-functional teams to integrate DFT features into the RTL design and ensure seamless validation and verification.
• Work closely with the STA methodology owner in defining hierarchical DFT constraints and multi-mode multi-corner sign-off.
• Produce area/power tradeoff against design choices made for improved DFT coverage.
• Own complete architecture, tool/vendor selection for DFT insertion, simulation, fault debug and characterization.
• Work closely with design, design-verification, and physical design teams to enable the integration and validation of test logic.
• Participate in the development of innovative hardware DFT and physical design aspects for new silicon device models.
• Create and maintain dashboards for tracking DFT collaterals to be handed over to Test Engineering, including coverage matrix.
• Responsible to produce a DFT architecture document for every PHY / chiplet programs specifying a detailed list of collaterals for customers.
• Work closely with physical implementation teams to define the optimal MMMC corners for various stages of implementation vis-à-vis placement, CTS and routing for DFT modes.
• Own the DFT architecture for 2.5D/3DIC multi-die products – hierarchical test access across base and stacked dies, die-to-die interconnect test, and IEEE 1838 / 1687 (IJTAG) based test infrastructure.
• Define Known-Good-Die (KGD) test and screening strategies for chiplets and hard IP, spanning pre-bond (wafer sort/probe), mid-bond and post-bond test content, and the stress/burn-in screens needed to hit KGD quality and DPPM targets.
• Architect DFT for die-to-die interfaces (Eliyan NuLink / BoW / UCIe-class PHYs), including at speed interconnect test, PHY loopback modes, lane repair and redundancy, and margining hooks for in-system diagnostics and yield recovery.
• Deliver chiplet- and IP-level DFT collateral that customers can drop into their own 3DIC test architectures – IEEE 1500-style test wrappers, retargetable pattern sets, and plug-and-play integration documentation. 

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• At least 15 years of experience in hardware DFT, testability, and physical design.
• Proven expertise in JTAG protocols, scan and BIST architectures, memory BIST, and boundary scan.
• Experience with ATPG and EDA tools (Tessent, TetraMax, Genus, Tempus, DC, PrimeTime)
• Experience with gate-level simulation, running SDF annotated simulations for test vector set
• Experience with post-silicon validation and debug, ATE patterns bring-up on Advantest ATEs.
• Hands-on DFT experience on 2.5D/3DIC and chiplet-based systems: multi-die test access architectures, pre-bond / mid-bond / post-bond test, TSV, micro-bump and hybrid-bond interconnect test, and die-to-die (UCIe / BoW class) interface test and loopback.
• Working knowledge of IEEE 1838 (3D test access), IEEE 1687 (IJTAG), and IEEE 1500 core test wrappers for hierarchical, pattern-retargetable IP and chiplet test.
• Demonstrated experience defining Known-Good-Die (KGD) screening and quality flows – wafer-level test content, DPPM/yield target setting, and stress or burn-in screening for die destined for advanced packaging.
• Experience delivering DFT collateral for licensable IP or chiplets to external customers, including test wrappers, retargetable patterns, coverage reports, and integration/hand-off documentation.
• Scripting skills in Tcl, Python, or Perl.
• Proven track record of being a highly visible contributor as part of a start-up like environment.
• Problem solver and efficient in written/verbal communication – excellent data organization skills and churns high-quality work product.
• Ability to work cross-functionally with digital, analog design, and implementation teams.