Top Tech Jobs & Startup Jobs

Design, implement, and optimize Linux kernel drivers and low-level userspace libraries for PCIe AI accelerators. Prototype and validate features on pre-silicon platforms, perform first-silicon bring-up, debug hardware/software interactions, profile host I/O paths, deliver tests, and expose telemetry for management and BMC integration while influencing future chip architecture.

The AI Accelerator Silicon Architect will define compute architecture, analyze performance, and collaborate with teams on silicon architecture for AI workloads.

As a Formal Verification Engineer, you will ensure correctness in hardware and software by applying model checking and developing machine-checked proofs, collaborating with various teams for verification processes.

The role involves silicon micro-architecture and design, managing the complete design process from micro-architecture to sign-off, including collaboration with verification teams and achieving high-performance metrics.

As a Silicon DFT Engineer, you will design test solutions, integrate DFT functions, collaborate with various teams, and improve test quality for AGI silicon.

Lead and drive design-phase execution for rack-scale AI platforms. Maintain master schedules, track critical-path items and risks, coordinate cross-functional design and readiness reviews, engage CM/JDM partners, ensure validation readiness, and provide executive updates on milestones, risks, and resource gaps.

Design, define, and validate rack-scale power architecture for a rack-scale AI data center product. Develop power specs and estimation models, implement and validate voltage regulator designs, perform lab bring-up and workload testing, ensure compliance with safety and thermal standards, and provide technical leadership during board and system integration.

Design and optimize hardware interfaces, collaborate with ML and hardware teams, and ensure software and hardware integration.

Develop and sign-off performant silicon from RTL to GDSII across blocks, subsystems, and full-chip. Lead partitioning, floorplanning, synthesis, P&R, clocking, verification, timing/power sign-off, and collaborate with Design, Verification, and DFT teams to meet tapeout milestones.

Lead integrated NPI lifecycle for rack- and board-level AI systems, coordinating CM/JDM partners, PLM/BOM/ECO control, factory test deployment, quality and yield metrics, and high-volume ramp readiness while reporting risks and readiness to executives.