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Owns major analog and power-management circuit blocks for complex PMIC and mixed-signal products from architecture through tape-out, silicon validation, and production. Leads CMOS circuit design, simulation, verification, layout supervision, feasibility studies, design reviews, and silicon characterization. Provides technical guidance and mentorship, collaborates across engineering functions, resolves production issues, develops reusable analog IP and design methods, and supports customer-facing technical discussions.

Manage strategic semiconductor customer accounts across Chicagoland and Indiana. Develop account plans and sales strategies, grow revenue and market share, build executive and cross-functional relationships, coordinate global teams, support customer manufacturing sites, provide demand forecasts, and help resolve supply issues. The role requires frequent regional travel, strong negotiation and communication skills, semiconductor product knowledge, and experience managing global customer relationships.

Designs and qualifies semiconductor package and interconnect technologies for power SiP/modules, flip-chip LGA, wafer-level packaging, and automotive and industrial applications. Develops materials and assembly processes with OSATs and contract manufacturers, runs optimization studies, establishes process controls and specifications, resolves integration and production issues, supports qualification and ramp-up, maintains package design rules, and contributes to technology roadmaps.

Owns technical readiness, manufacturability, qualification, and lifecycle performance of advanced semiconductor power modules from NPI through high-volume production. Leads assembly process development, product bring-up, yield and parametric analysis, defect investigations, manufacturing release, change management, and production issue resolution. Partners with design, test, quality, manufacturing, applications, OSATs, and customers to improve performance, quality, cost, yield, and cycle time.

Develops and validates Renesas memory interface products from conception through production release. Responsibilities include post-silicon application support, hardware and software lab validation, high-speed test board design and debugging, test automation, customer problem-solving, application documentation, and collaboration with design, test, quality, and other engineering teams. The role focuses on DDR and SERDES technologies, computer system architecture, and optimizing semiconductor performance in customer applications.

Leads digital design for power management ICs across requirements, architecture, RTL implementation, verification, debugging, simulation, and automation. Develops Verilog and SystemVerilog designs, tests, and scripts; supports pre- and post-silicon validation; evaluates design tools; and manages assigned blocks. Provides technical leadership, mentors junior engineers, and represents digital design on project teams.

Lead design and integration of low-power, area-optimized digital RTL for mixed-signal data conversion and power-management ASICs. Own full product lifecycle from architecture through silicon bring-up, collaborate with analog, verification, and P&R teams, run RTL/gate-level simulations, define constraints, support DFT and STA, mentor engineers, and drive design reviews, documentation, and silicon debug.

Lead and contribute to analog design for complex CMOS power management ICs. Provide technical leadership for major blocks, supervise design, simulation, and layout, guide products into production, and lead feasibility studies, lab evaluation, verification, and test development. Mentor engineers, drive design-methodology improvements, support DFT, collaborate with cross-functional teams and customers, and contribute to RFQ activities and technical documentation.

Define, evaluate, and architect PMIC designs and industry standards. Drive mixed-signal simulations and lab evaluations, support silicon bring-up, circuit debugging, production test development, documentation, and customer/applications support. Specify future technology requirements and collaborate with cross-functional teams to enable world-class power management products.

Creates and verifies top-level, cell-level, analog, mixed-signal, power, and digital IC layouts for radiation-hardened semiconductor products. Responsibilities include floorplanning, routing, package bond diagrams, physical verification, mask data release, archiving, and collaboration with circuit designers and CAD teams. The role requires extensive experience with Cadence layout tools, BCD and SOI processes, and IC layout methodologies.