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The Principal Quality Assurance Engineer ensures product quality and reliability by executing product qualifications, implementing stress tests, and collaborating across functions. Responsibilities include risk assessments, handling qualification issues, generating reports, and driving product robustness initiatives.

The Product Designer creates intuitive user experiences by analyzing workflows, conducting user research, and collaborating with cross-functional teams to develop and prototype designs, particularly for complex engineering tools.

Lead a design team focusing on Power Management IC development, participating in product definition, design validation, and team management to achieve schedule objectives.

As a Senior Firmware Verification Engineer, you will validate firmware for power management ICs, develop testbenches, run simulations, and collaborate with engineering teams.

Lead a team of analog designers in developing configurable mixed-signal ASICs, overseeing project technical aspects from concept through market release, and collaborating cross-functionally.

As a Senior System & Application Engineer, you will define and validate power product solutions for AI server markets, interfacing with customers and collaborating with teams to develop power architectures, perform analysis, and create documentation.

Manage Oracle, SQL Server, and PostgreSQL databases, ensuring performance and security. Analyze issues, implement automation processes, and design documentation for database management.

As a Principal Product Definition Engineer, you'll drive product and system definition for high-performance power solutions, collaborating with multiple teams to meet customer requirements and support market adoption.

The Staff Strategic Planning Specialist analyzes market trends, supports executives with data-driven insights, manages strategic projects, and fosters cross-functional collaboration to enhance operational efficiency at Renesas Power Product Group.

The intern will research PMIC control architecture and assist in simulations and circuit building using Cadence, supporting the development of next-gen DDR PMIC.