Top Tech Jobs & Startup Jobs

Develop test methodologies and requirements for radiation-hardened semiconductor ICs used in space applications. Responsibilities include writing characterization and production test programs, designing ATE load boards, defining test schematics and hardware, debugging test solutions, correlating production tests with bench measurements, performing GR&R and transient analyses, and transferring solutions to production.

Technical leader driving next-generation Intelligent Power Device design and delivery. Lead cross-functional teams through concept to production, define system architectures, ensure automotive reliability and ISO 26262 compliance, drive verification and test strategies, mitigate silicon and system risks, and mentor engineers.

Drive revenue growth and market share for Renesas semiconductor solutions across AI, humanoid robotics, physical AI, edge computing, and IoT markets in the San Francisco Bay Area. Responsibilities include strategic account planning, customer and executive relationship management, cross-selling embedded, analog, power, and software solutions, developing design wins, managing forecasts and pipelines, negotiating agreements, and providing market intelligence to guide product and business strategy.

Lead root-cause investigations for automotive PMIC field failures from RMA intake through FA and resolution. Reproduce issues, collect waveforms, run analog simulations, review RTL/netlist, coordinate FA lab work, propose fixes or workarounds, produce customer-facing technical reports (8D, RCA), and drive cross-functional handoffs and design improvements.

Design and implement digital DFT (scan, ATPG, LogicBIST) for automotive PMICs, improve scan coverage, create and validate test patterns, run gate-level simulations, support synthesis/P&R/timing, and collaborate with architects, test, and validation teams to meet ASIL requirements.

The Senior Principal System Engineer will lead customer interactions, define product specifications for Power ICs, mentor junior engineers, and ensure timely project deliveries while addressing technical challenges across engineering teams.

Lead design and integration of low-power, area-optimized digital RTL for mixed-signal data conversion and power-management ASICs. Own full product lifecycle from architecture through silicon bring-up, collaborate with analog, verification, and P&R teams, run RTL/gate-level simulations, define constraints, support DFT and STA, mentor engineers, and drive design reviews, documentation, and silicon debug.

Lead analog CMOS power-management block design from specification through production: architecture, simulation, layout supervision, lab evaluation, test/DFT strategy, verification planning, mentoring, and customer-facing support to ramp products.

Define, evaluate, and architect PMIC designs and industry standards. Drive mixed-signal simulations and lab evaluations, support silicon bring-up, circuit debugging, production test development, documentation, and customer/applications support. Specify future technology requirements and collaborate with cross-functional teams to enable world-class power management products.