Top Tech Jobs & Startup Jobs

Serve as trusted technical consultant for enterprise customers: run value-assessment workshops, recommend Altium/ECAD/PLM solutions, build business cases, create executive content, coordinate cross-functional delivery, and present value to decision-makers. Regular onsite travel to US/Europe.

Manage a major semiconductor account by building stakeholder relationships, qualifying requirements, presenting product roadmaps and demos, driving design-wins, coordinating RFQ responses with internal teams, tracking pipeline and forecasts, and identifying account expansion opportunities while staying current on customer roadmaps and competitive trends.

Responsible for verifying DDR6 data buffer chips, developing verification plans, test strategies, and optimizing verification environments using UVM methodology.

Lead the development of DDR5 and DDR6 PHY solutions, managing a team focused on high-speed memory interfaces, overseeing design and implementation, ensuring compliance with standards, and fostering technical excellence.

The Principal Digital Verification Engineer is responsible for verifying DDR5 Data Buffers, developing verification plans, creating reusable test environments, and leading a team in memory interface product verification for optimal performance and quality.

Manage global product marketing for memory interface products targeting AI datacenters. Drive business growth, develop business cases, and collaborate with R&D and sales teams to meet customer needs.

The role involves verifying DDR5 Data Buffer chips, developing verification plans, and optimizing test environments while mentoring a team of engineers.

Lead package technology development and NPI for power packaging (SiP/modules, wafer‑level, flip‑chip), manage OSAT/CM relationships, qualify materials/processes, define roadmap and design rules, and ensure production ramp, quality, and customer adoption.

Define and drive end-to-end embedded firmware architecture for AI cluster scale-up switches. Design low-level firmware for ASIC microcontrollers, hardware-software interfaces, link training, topology discovery, routing, and flow-control. Optimize latency/bandwidth, implement RAS features and secure boot/root-of-trust, and lead SDK/API design for BMC integration (OpenBMC/Redfish). Collaborate with ASIC, RTL, and verification teams and use hardware debug and lab tools to validate high-speed fabric performance.

Senior technical authority defining and governing physical-design architecture and foundry strategy (TSMC) for MCU/SoC products. Leads AI initiatives to reduce MCU development cost, drives physical partitioning, PPA targets, IO and timing requirements, and aligns die-size and KPI goals with system architects and chip leads.