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Reposted One Month AgoSaved
In-Office
3 Locations
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.
Top Skills: PerlPythonSpice ModelingSta ToolsTcl
Reposted One Month AgoSaved
In-Office
3 Locations
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.
Top Skills: PerlPythonRedhawkShellTclVoltus
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