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The role involves full-custom layout of mixed-signal ICs, focusing on performance and integration into SoCs using advanced FinFET processes.

Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.

The role involves CPU core verification for out-of-order RISC-V CPUs, requiring in-depth microarchitecture knowledge and development/debugging of functional verification models.

The PCB Layout Engineer will design multi-layer PCB layouts for high-performance computing and AI hardware, ensuring specifications for mass production. Responsibilities include routing high-speed interfaces and collaborating with cross-functional teams to meet design requirements.

Drive top-level implementation of complex AI and CPU SoC designs, ensuring design closure and optimizing chip-level implementations for power, performance, and area.

The Design for Test Engineer will implement DFT features in RTL, analyze test coverage, and support silicon bring-up for advanced AI/ML architectures.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.