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The engineer will join a CPU design team focusing on performance analysis, verification, and collaboration with architects to deliver efficient CPU designs using RISC-V ISA.

Partner with the C-suite to execute M&A, lead financial and business modeling for deals and fundraising, build/manage strategic partnerships across AI/semiconductor/data center ecosystems, prepare board-level strategy materials, and support government relations and stakeholder engagement.

Design and implement chip-level DFT strategies for high-speed CPU cores and multi-chiplet SiP. Implement and verify scan chains, memory BIST, and JTAG. Partner with RTL, physical design, and verification teams. Script and automate DFT flows using EDA tools (ATPG, fault coverage) and support SoC-level silicon debug, formal verification, and DFT signoff.

Shape and evaluate next-generation high-performance RISC-V CPUs using performance modeling and simulation. Build and run architectural models (Gem5/SST/SimpleScalar), analyze pipelines, caches, branch prediction, and memory hierarchies, implement modeling and analysis tools in C++/Python, and collaborate with CPU architects to optimize AI/HPC workload performance. Hybrid role based in Santa Clara or Austin.

Own the flagship data-center AI compute product line: define topology, cabling, power, and orchestration; coordinate engineering, manufacturing, CX and sales; ensure reliable deployments in colos and customer data centers; support hardware, software, and firmware in the field; travel for installs and customer engagements; drive uptime, scaling, and total cost of ownership improvements.

Own and drive end-to-end product certification and regulatory compliance to enable customer shipments and revenue. Coordinate Sales, Systems Engineering, Operations, Manufacturing, and external agencies; remove roadblocks, manage escalations, track timelines and risks, and ensure products meet global import/export and regional regulatory requirements.

Lead end-to-end software development for a chiplet-based SiP across pre- and post-silicon stages. Manage multi-year roadmaps, 40+ engineers and external vendors, define success metrics, implement shift-left strategies, integrate vendor software (PCIe, D2D, Ethernet), establish CI/CD and testing, and communicate progress and tradeoffs to executives and stakeholders.

Lead and grow a software engineering team focused on RISC-V software ecosystem, collaborating with teams to establish RISC-V as the standard.

Responsible for physical design of high-performance CPUs and AI/ML architectures, including implementation from synthesis to tapeout, and collaborating with front-end teams.

The Project Manager will oversee People initiatives, ensuring smooth execution of promotions, performance, and surveys while coordinating cross-departmental communication and tracking progress.