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The role involves bridging pre-silicon and post-silicon verification by debugging silicon issues and working with emulation platforms to accelerate AI SoC development.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

Manage corporate infrastructure for global office projects, ensuring integration of AV and IT systems, overseeing contractors, and leading project delivery.

The Staff DevOps Engineer will optimize infrastructure for chip development, build CI/CD pipelines, and enhance workflows using AI/ML practices.

The CPU Workload Performance Analysis Engineer will conduct workload characterization and performance simulation to optimize CPU products, collaborating with architects and designers.

The Field Application Engineer will serve as the primary technical contact for customers, focusing on implementing AI/ML hardware/software solutions, collaborating with teams, and ensuring customer success.

As a CPU Microarchitecture/RTL Engineer, you will design high-performance CPUs, focusing on RTL design and microarchitecture collaboration with cross-functional teams.

Lead the physical design of high-performance CPUs and AI/ML chips, managing backend execution from RTL handoff to tapeout, while collaborating with various teams to optimize power, performance, and area.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Manage global supply chain strategies for custom silicon products, optimizing performance through collaboration with engineering, logistics, and suppliers.