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Own end-to-end physical implementation of AI accelerator and RISC-V IP blocks from synthesis through PnR, timing closure, and GDSII signoff. Drive PPA outcomes, collaborate with RTL owners, build floorplans, power grids, pin placement and clocking strategies, and deliver LEF/DEF, timing and power models, GDS, and signoff reports for tapeouts on advanced nodes.

As a Full-Chip Physical Design Verification Engineer, you will ensure manufacturable silicon by driving full-chip signoff, leading physical verification closure, and collaborating with various teams to achieve successful tapeouts.

The AI Subsystems Physical Design Lead is responsible for timing for subsystems in an AI chip, collaborating with RTL designers, and involved in synthesis, place and route, timing analysis, and power optimization.

The Physical Design Engineer will implement high-performance blocks for CPUs and AI/ML architectures, overseeing the entire flow from synthesis to tapeout and collaborating closely with teams to optimize performance, power, and area.

Lead go-to-market positioning and messaging for Tenstorrent's AI hardware and software stack. Develop application- and vertical-specific value propositions, technical collateral (whitepapers, benchmarks, demos, sales decks), and field enablement. Partner closely with product, engineering, sales, and marketing to align roadmap, launches, and customer solutions. Translate technical capabilities into business value for enterprise, cloud, and regulated markets while gathering customer and competitive insights to inform strategy.

Lead go-to-market positioning and solution strategy for Tenstorrent's AI hardware and software stack. Develop application- and vertical-specific value propositions, technical collateral (whitepapers, decks, benchmarks, demos), and customer stories. Partner with product, engineering, sales, and marketing to align roadmaps, launches, and field enablement, translating deep technical capability into clear customer outcomes.

Lead and deliver an end-to-end ERP implementation: define scope, milestones, governance; manage external consultants and SOWs; coordinate Sales, Supply Chain, Finance, Trade, Infosec, Engineering, and Solution Architecture; use PM tools and AI-enabled documentation to track actions, report status, and mitigate risks and dependencies.

Lead architecture and microarchitecture of RISC-V CPU vector, floating-point, and matrix extensions. Translate HPC/AI workload needs into scalable CPU designs, optimize performance/power/area, define architectural specs, lead cross-functional teams from concept through silicon, and work on RTL development to enable efficient heterogeneous compute for AI/HPC.

Lead R&D on LLM training and inference optimization, train and evaluate large-scale models on Tenstorrent hardware, improve performance via techniques like speculative decoding, quantization, kernel fusion, flash attention and distributed training, diagnose system bottlenecks, and translate research into scalable production solutions through cross-functional collaboration.

As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.