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Reposted 21 Days AgoSaved
In-Office
Austin, TX, USA
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
Lead customer engagements for RISC-V CPU server and machine learning processor projects, coordinating with engineering teams and managing technical program requirements.
Top Skills: AICpuIpRisc-VSoc
Reposted 21 Days AgoSaved
In-Office
3 Locations
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
Lead post-silicon power characterization and correlation for semiconductor products, develop measurement strategies, and improve power architectures to meet specifications.
Top Skills: Current ProbesMatlabOscilloscopesPerlPower AnalyzersPythonRisc-VSmus
Reposted 21 Days AgoSaved
In-Office
3 Locations
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.
Top Skills: Ai/MlEda ToolsFusion CompilerGdsPythonPyTorchRtlTclTensorFlow
Reposted 21 Days AgoSaved
In-Office
2 Locations
100K-500K Annually
Junior
100K-500K Annually
Junior
Hardware • Manufacturing
As a SOC Emulation Engineer, you'll support hardware emulation infrastructure, integrating hardware transactors and developing Python-based test frameworks while providing technical support across chip projects.
Top Skills: C++PythonSynopsys ZebuSystemverilog
Reposted 23 Days AgoSaved
In-Office
3 Locations
100K-500K Annually
Mid level
100K-500K Annually
Mid level
Hardware • Manufacturing
As a Senior Software Engineer at Tenstorrent, you will develop AI compiler technologies, optimize computational graphs, and enhance MLIR frameworks to connect AI models with hardware.
Top Skills: C++JaxMlirPythonPyTorchTensorFlow
Reposted 23 Days AgoSaved
In-Office
3 Locations
100K-500K Annually
Senior level
100K-500K Annually
Senior level
Hardware • Manufacturing
The SoC Physical Design Verification Engineer leads full-chip signoff, ensuring high-quality silicon through physical verification and debugging across teams for successful tapeouts.
Top Skills: CalibreFcIcvInnovusPegasusPythonTcl
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