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Lead go-to-market positioning and solution strategy for Tenstorrent's AI hardware and software stack. Develop application- and vertical-specific value propositions, technical collateral (whitepapers, decks, benchmarks, demos), and customer stories. Partner with product, engineering, sales, and marketing to align roadmaps, launches, and field enablement, translating deep technical capability into clear customer outcomes.

Lead and deliver an end-to-end ERP implementation: define scope, milestones, governance; manage external consultants and SOWs; coordinate Sales, Supply Chain, Finance, Trade, Infosec, Engineering, and Solution Architecture; use PM tools and AI-enabled documentation to track actions, report status, and mitigate risks and dependencies.

Lead architecture and microarchitecture of RISC-V CPU vector, floating-point, and matrix extensions. Translate HPC/AI workload needs into scalable CPU designs, optimize performance/power/area, define architectural specs, lead cross-functional teams from concept through silicon, and work on RTL development to enable efficient heterogeneous compute for AI/HPC.

Lead R&D on LLM training and inference optimization, train and evaluate large-scale models on Tenstorrent hardware, improve performance via techniques like speculative decoding, quantization, kernel fusion, flash attention and distributed training, diagnose system bottlenecks, and translate research into scalable production solutions through cross-functional collaboration.

As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.

The Performance Architect will work on high-performance systems with expertise in software and hardware, focusing on AI and HPC solutions.

Design, implement, and maintain TT-Fabric, a low-level high-performance networking library for large-scale AI clusters. Build scalable communication protocols, optimize synchronization and data movement for thousands of processors, integrate APIs with AI and hardware teams, and help define the distributed systems architecture to maximize hardware performance.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

Lead CPU core-level testbench development and verification for high-performance out-of-order RISC-V CPUs, involving hands-on infrastructure development and debugging using AI methodologies.

Lead customer engagements for RISC-V CPU server and machine learning processor projects, coordinating with engineering teams and managing technical program requirements.