Top Tech Jobs & Startup Jobs

Lead the development of AI compiler tools, enhance performance analysis, collaborate with hardware teams, and mentor engineers to improve compiler tooling.

Develop and maintain infrastructure platforms for AI services, build APIs, manage Kubernetes clusters, and automate workflows using CI/CD practices.

Select and qualify electronic components for high-performance AI compute systems, maintain Approved Vendor List, drive multi-sourcing and cost optimization, monitor lifecycle and supplier risk, and collaborate with hardware, procurement, and supply teams to ensure component availability for scalable production.

Own end-to-end electronics components and PCB supply chain, managing suppliers (CMs, PCB fabs, distributors), supporting NPI and production ramps, aligning forecasts, negotiating multi-year contracts, and mitigating supply risks to ensure product availability and revenue.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.

Lead and enhance global People Operations, focusing on employee lifecycle management, operational excellence, and compliance across multiple regions.

As a Chip Design Lead at Tenstorrent, you will oversee the development of SoC programs from architecture to deployment, ensuring collaboration across teams and managing chip lifecycle processes.

The engineer will join a CPU design team focusing on performance analysis, verification, and collaboration with architects to deliver efficient CPU designs using RISC-V ISA.

Partner with the C-suite to execute M&A, lead financial and business modeling for deals and fundraising, build/manage strategic partnerships across AI/semiconductor/data center ecosystems, prepare board-level strategy materials, and support government relations and stakeholder engagement.

Design and implement chip-level DFT strategies for high-speed CPU cores and multi-chiplet SiP. Implement and verify scan chains, memory BIST, and JTAG. Partner with RTL, physical design, and verification teams. Script and automate DFT flows using EDA tools (ATPG, fault coverage) and support SoC-level silicon debug, formal verification, and DFT signoff.