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Silicon Labs

Design Engineer I

18 Days AgoSaved

In-Office

Austin, TX, USA

79K-146K Annually

Entry level

79K-146K Annually

Entry level

Hardware • Software

Support physical implementation from RTL through GDSII/tapeout: develop and maintain SDC timing constraints, perform STA across conditions, assist signoff, analyze timing reports, debug implementation and integration issues, and improve physical implementation flows and automation while collaborating with cross-functional teams.

Top Skills: Cadence TempusEda Tool FlowsGdsiiLinuxPerlPythonRtlSdc (Timing Constraints)Static Timing Analysis (Sta)Synopsys PrimetimeTapeoutTclUnix

Silicon Labs

Associate Staff Analog Design Engineer

Reposted 23 Days AgoSaved

In-Office

Austin, TX, USA

125K-231K Annually

Senior level

125K-231K Annually

Senior level

Hardware • Software

Develop wireless communication ICs for IoT applications, design and validate analog/mixed-signal circuits, and lead technical teams in chip design projects.

Top Skills: MatlabPerlSkillTclUnixVerilogVeriloga

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