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Responsible for defining qualification strategies for AI compute platforms, ensuring hardware reliability through testing, failure analysis, and collaboration across teams.

The Senior Staff Signal Integrity Engineer drives SI/PI strategy for AI accelerators, leads modeling/simulation, optimizes power delivery networks, and provides technical mentorship.

Responsible for demand and supply planning for server systems, managing partner contracts, and ensuring inventory and customer order fulfillment through cross-functional collaboration.

Design and analyze analog-mixed signal integrated circuits for AI inference accelerators, focusing on circuit design, performance analysis, simulations, and collaborating with layout and backend engineers.

Responsible for power estimation, architectural tool development for AI workloads, and optimizing performance monitoring in micro-architecture and RTL. Collaborate with teams for design integration and silicon validation.

The intern will design and implement AI solutions for manufacturing workflows, focusing on LLMs to improve operational efficiency, data management, and collaboration across teams.

As a Compiler Architect, you'll design and implement a scalable MLIR-based compiler for cloud-based AI inference, focusing on optimizing large-scale AI models and architecting efficient software pipelines for deployment.

As a Principal Software Engineer, you will develop and maintain software kernels for AI hardware, collaborating on full-stack optimization and compiler infrastructure.

As a Software Engineer at d-Matrix, you will design and develop diagnostic tools for AI inference accelerators, enhancing the toolset for hardware validation.

Lead SoC architecture definition and delivery for AI accelerators. Analyze AI workloads, drive hardware/software co-design, performance modeling, simulation tools, kernel and networking fabric work, port and optimize customer workloads, and collaborate across RTL, DV, and software teams.