Systems Hardware Engineer, Principal

Reposted 3 Days Ago
Be an Early Applicant
Santa Clara, CA, USA
Hybrid
150K-300K Annually
Expert/Leader
Artificial Intelligence • Machine Learning • Software
The Role
Lead the hardware development for AI accelerator platforms, focusing on high-performance designs, cross-functional collaboration, and mentorship of junior engineers.
Summary Generated by Built In

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. 

Location:

Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week.

About the Role

At d-matrix, we are redefining the architecture of AI compute. As a Principal Hardware Design Engineer, you will be a cornerstone of our hardware organization, leading the development of world-class platforms for our silicon-integrated AI accelerators. You aren’t just "designing boards"; you are architecting the physical foundation that allows our Chiplet-based NPU (Neural Processing Unit) to solve the industry's most massive LLM inference challenges.

Required Qualifications

• Education: BS/MS in Electrical Engineering or a related field.

• Experience: 10+ years of experience in high-complexity hardware design, specifically within the semiconductor, server, or networking industries.

• Board Design: Mastery of Cadence Allegro/Orcad or similar high-end EDA tools.

• Power & Signal Integrity: Deep understanding of SI/PI fundamentals, including jitter, crosstalk, and impedance control for 32Gbps+ signals.

• Laboratory Skills: Proficiency with high-speed oscilloscopes, BERTs, and VNA/TDR for hardware bring-up and validation.

• Communication: Ability to distill complex technical trade-offs into actionable decisions for executive leadership.

Preferred Skills

• Experience with OCP (Open Compute Project) standards or large-scale data center deployments.

• Knowledge of liquid cooling integration for high-TDP hardware.

• Nice to have: Familiarity with FPGA prototyping and emulation platforms.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Skills Required

  • BS/MS in Electrical Engineering or a related field
  • 10+ years of experience in high-complexity hardware design
  • Mastery of Cadence Allegro/Orcad or similar high-end EDA tools
  • Deep understanding of SI/PI fundamentals for 32Gbps+ signals
  • Proficiency with high-speed oscilloscopes, BERTs, and VNA/TDR
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The Company
HQ: Santa Clara, CA
102 Employees

What We Do

d-Matrix is building a new way of doing datacenter AI inferencing using in-memory computing (IMC) techniques with chiplet level scale-out interconnects. Founded in 2019, d-Matrix has attacked the physics of memory-compute integration using innovative circuit techniques, ML tools, software and algorithms; solving the memory-compute integration problem, which is the final frontier in AI compute efficiency.

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