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5 Days Ago
Santa Clara, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning
Celestial AI is seeking a Package Reliability Engineer to conduct reliability analysis, manage OSAT collaborations, and perform failure analysis for 2.5D/3D advanced packaging. The role involves evaluating materials, developing stress test plans, and ensuring compliance with industry standards to enhance package manufacturability and reliability.
Top Skills: AbaqusAnsysC-SamComsolEbsdFibSemTemX-Ray Ct
5 Days Ago
2 Locations
Senior level
Senior level
Artificial Intelligence • Machine Learning
As a Digital Design Engineer, you will design, implement, and optimize DSP algorithms for high-speed communication systems, collaborating with cross-functional teams. The role involves algorithm optimization, simulation using MATLAB/Simulink, and integrating DSP algorithms into larger systems.
Top Skills: MatlabSimulinkSystem Verilog
7 Days Ago
Santa Clara, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning
The Senior SoC Design and Integration Engineer will drive SoC design, integration, and implementation, focusing on high-speed interfaces and ASIC execution. Responsibilities include RTL design, IP verification, and working closely with teams for seamless SoC bring-up and debugging. Candidates should have strong problem-solving skills and collaborate across multiple teams to validate and integrate SoCs effectively.
12 Days Ago
Santa Clara, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning
The Mixed-Signal Verification Engineer will develop and maintain mixed-signal ASIC simulation environments, collaborate with design teams, analyze system-level performance, create simulation test plans, and support silicon validation efforts by correlating simulation results with lab measurements.
Top Skills: Analog SimulationMixed-Signal AsicsMixed-Signal Simulation ToolsPythonSystemverilogTclVerilog-A
12 Days Ago
Santa Clara, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning
As a Senior Firmware Architect, you will lead the architecture and development lifecycle of an AI platform using Celestial AI's Photonic Fabric. Responsibilities include defining firmware architecture and APIs, collaborating with hardware and software teams, participating in requirements gathering, and ensuring code quality through reviews and documentation.
Top Skills: ArmAxiC/C++DdrEmbedded LinuxEthernetFibre ChannelHbmI2CInfinibandJtagLinuxPciePythonRdmaRtosRustSpiUartX86
12 Days Ago
Santa Clara, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning
The Senior ASIC/VLSI Synthesis and Design Engineer will develop high-performance, low-power digital designs for ASICs and SoCs, focusing on optimizing power, performance, and area, ensuring timing closure, and conducting post-silicon validation. This role includes collaboration with cross-functional teams, implementing synthesis methodologies, and performing power analysis.
Top Skills: AsicCadenceConformal LecDcEda ToolsGenusMentorPerlPrimetimePythonSynopsysSystemverilogTclTempusVerilogVlsi
Reposted 13 Days Ago
Santa Clara, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning
As a Chiplet Design Verification Lead, you'll oversee verification strategy and execution for complex IP, manage a team of verification engineers, and collaborate with architects and design teams to ensure successful product releases. Your responsibilities include defining verification plans and leading the verification of a complex 5nm SoC with high-speed interfaces.
Reposted 13 Days Ago
Santa Clara, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning
The SoC Design Verification Lead will lead the verification strategy and execution for complex 5nm SoCs, collaborating with architects and design engineers, reviewing verification test plans, and mentoring a team of engineers. This role is crucial for ensuring successful product releases and first-pass tapeout success.
Reposted 13 Days Ago
Santa Clara, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning
The Photonics Layout Engineer will design layouts for Silicon Photonic chips and contribute to their delivery from floor-planning to verification. The engineer will collaborate with analog, digital, and packaging teams to ensure design meets product requirements, while optimizing layout flows and enhancing design automation.
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