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Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, build testbenches, assertions, and coverage models, perform root-cause debug, work with architecture/RTL/performance teams, and drive verification closure and reusable methodology across core generations.

Lead functional verification for high-performance out-of-order CPU cores. Plan and execute block-to-core verification, develop UVM/SystemVerilog testbenches, write coverage and assertions, create constrained-random and directed tests, debug failures, collaborate with architects and RTL teams, and contribute reusable DV methodology and infrastructure to achieve signoff-quality verification.

Lead verification planning and execution for high-performance out-of-order CPU core blocks (frontend, midcore, LSU, prefetch). Define verification strategies, develop environments, assertions, scoreboards, stimulus and coverage models, perform root-cause debug, partner with architecture and design teams, and deliver reusable methodology to close microarchitectural risks and achieve signoff.

Drive functional verification for high-performance out-of-order CPU cores: create verification plans, develop UVM/SystemVerilog testbenches, write assertions and coverage, run constrained-random and directed tests, analyze/debug failures, and build reusable DV methodology and infrastructure to achieve verification signoff.

Develop and maintain a scalable Verification Platform: extend Chisel/CIRCT, build Scala libraries and Python tools for test harnesses, stimulus, and metadata querying, support end-to-end verification flows, and educate DV teams on best practices.