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Design and implement debug, trace, and profiling hardware, collaborate with cross-functional teams, and lead improvements in hardware design processes.

The SOC Architect will lead the development of high-performance SoCs, defining security features, and collaborating with product teams and customers to deliver system IPs.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel). Integrate designs into SiFive's Chisel/FIRRTL framework, enable automatic configuration, verification, and documentation, and collaborate with verification teams and peers to deliver high-performance, configurable interconnect IP.

The Executive Business Partner / Assistant will support the CTO and EVP Engineering with executive tasks, business operations, strategic support, and communication, managing complex calendars and travel while driving operational efficiency.

As a Datacenter System Software Architect at SiFive, you'll design RISC-V Linux systems for datacenters, engage with customers, and optimize performance across software and hardware.

The Strategic Sales Director is responsible for creating account plans, developing customer relations, and achieving sales targets within semiconductor companies. They must possess extensive experience in sales, specifically in IP sales, and be able to communicate effectively with clients.

Architect, design and implement features for RISC-V CPU core generators using Chisel, with responsibilities in verification and performance modeling, collaborating with teams.

The role involves analyzing and optimizing power consumption in SiFive IP, guiding architecture for power efficiency, and improving power analysis flows.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

Lead verification strategy and execution for CPU-subsystem power-management across unit, subsystem, and signoff levels. Define tests, assertions, coverage, and corner-case stress scenarios for DVFS, retention, clock/reset sequencing, power gating, and multi-domain interactions. Drive debug, root-cause analysis, formal and power-aware methods, reusable infrastructure, and mentor engineers to achieve data-center-grade signoff readiness.