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Supports sales representatives, headquarters, and customers by managing orders, verifying pricing, expediting shipments, resolving credit issues, processing returns and samples, entering demand forecasts, invoicing through SAP, and preparing management reports. The role also handles customer inquiries, accounts receivable monitoring, and month-end standby support. Daily onsite presence in San Jose, California is required.

Develops black-box functional tests and methodologies for NVMe SSDs, debugs and triages firmware failures, reproduces issues, and designs experiments with firmware teams. Analyzes customer field problems to close test coverage gaps, guides automation integration, and collaborates with global customers, OEMs, and distributed engineering teams. The role requires programming and scripting expertise, Linux and storage knowledge, embedded software or firmware testing experience, and familiarity with PCI protocol analyzers and storage test tools.

Lead AI workload characterization and storage architecture for large-scale inference, RAG, and training systems. Analyze performance across inference runtimes, Linux storage and networking, SSD hardware, and GPU infrastructure. Drive data-placement strategies, modeling, benchmarking, customer proofs of concept, standards engagement, cross-functional architecture decisions, and technical mentorship. The role focuses on integrating AI data paths with NAND, SSD, NVMe, and networked storage systems.

The Director of Design Verification will oversee SoC verification processes, manage engineering teams, and collaborate across departments to enhance memory and storage capabilities, ensuring first-pass silicon success.

Develop verification infrastructure for AI accelerator IP blocks, create testbenches, mentor junior engineers, and debug across teams.

The role involves developing advanced location technologies, optimizing receiver models, designing algorithms for GNSS systems, and collaborating with various engineering teams. Responsibilities include simulation, testing, and performance analysis of location IP products.

Design and simulate high-speed analog and mixed-signal circuits (PLL, SERDES, data converters), own circuit/system specs, guide and supervise layout, collaborate with verification and process teams, perform silicon bring-up and scripted measurements, and document results to meet PPA targets.

Provide hands-on DRAM application engineering support: validate and troubleshoot memory on server platforms, perform SI/PI and timing measurements, run joint customer validations and self-qualification, develop experiments and automation tooling, communicate findings, and coordinate with internal R&D and external teams to resolve memory/system issues.

Develop and support enterprise and data center SSD products by analyzing the full PCIe stack from PHY through Transaction layers. Own link training, LTSSM behavior, enumeration, equalization, flow control, replay, error handling, and data integrity. Debug and optimize PCIe issues across Gen1–Gen7 during product bring-up and sustaining, support compliance testing and PCI-SIG events, and provide onsite customer support. The role requires collaboration with hardware teams and vendors and up to 25% travel.

Provides executive and administrative support through calendar management, travel coordination, expense reconciliation, visitor logistics, bilingual Korean-English communication, and documentation maintenance. Manages R&D budgets, procurement, lab assets, software licenses, business requests, onboarding, offboarding, resource allocation, workshops, and cross-functional action items. Serves as a primary administrative contact for an AI/ML engineering organization and supports operational efficiency across Finance, Procurement, HR, IT, and facilities.