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Lead application engineering for semiconductor PCIe/CXL products: support ODM design-in, debug silicon/system bring-up in lab and customer environments, create technical collateral, drive issue resolution with internal teams and customers, and provide on-site global support.

Develop and maintain embedded C/C++ firmware for analog and Ethernet connectivity devices, perform low-level hardware bring-up and debugging, write Python test automation, collaborate on validation and CI tooling, participate in code reviews and project tracking, and characterize firmware behavior across operating conditions.

The Senior VLSI Design Engineer will design and implement digital blocks for complex semiconductor chips, tackling logic challenges and ensuring robust performance in AI infrastructure solutions.

As a Senior Physical Design Engineer, you will oversee the physical implementation of complex semiconductor designs and guarantee their performance and integrity.

The Principal Product Application Engineer will lead firmware development and customer engagement for CXL Smart Memory Controllers, ensuring seamless integration and resolution of firmware issues while collaborating with various engineering teams.

The Principal Emulation Engineer will verify protocols on ASICs, create testing environments, and debug hardware-software interfaces, focusing on communication protocols like PCIe and Ethernet.

The Senior Emulation Engineer will execute emulation flows, debug and validate semiconductor chips, and collaborate with cross-functional teams to enhance hardware-software integration.

Lead and develop next-generation high-speed semiconductor products, focusing on product and test engineering, circuit design, and problem-solving.

Lead global supplier and customer quality for semiconductor, board-level, optical, and rack-scale products. Drive failure analysis, audits, corrective actions, supplier onboarding, KPI systems, and advanced data analytics to predict and mitigate quality and supply risks. Interface with customers, conduct containment and recovery, and collaborate cross-functionally to ensure manufacturability and product quality.

Lead and execute RTL-to-GDS physical implementation for advanced-node connectivity SoCs: floorplan, placement, CTS, routing, timing/power signoff, verification, ECO/tapeout, and mentor engineers while partnering cross-functionally to define methodology and ensure production-quality deliverables.