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Reposted 7 Days AgoSaved
In-Office
San Jose, CA, USA
230K-265K Annually
Expert/Leader
230K-265K Annually
Expert/Leader
Big Data • Information Technology
Lead DFT strategy and execution for multi-die PCIe switch products using 2.5D/3D packaging. Define test architecture, implement scan/ATPG/MBIST/LBIST, drive fault coverage targets, optimize production test and ATE costs, collaborate across design, packaging, validation, and manufacturing to ensure yield, reliability, and production ramp.
Top Skills: 2.5D Packaging3D IntegrationAdvantest AteAibBowChiplet ArchitecturesCowosCxlDftmaxEmibEthernetHbmHigh-Speed Serdes BistHybrid BondingIeee 1149.1 (Jtag)Ieee 1687 (Ijtag)Ieee 1838 (3D-Dft)Jesd229Jesd235Kgd StrategiesLbistMbistMentor TessentMicro-BumpNvlinkPcie (Gen3/4/5/6)Synopsys Dft CompilerTeradyne AteTetramaxTsvUalinkUcie
Reposted 7 Days AgoSaved
In-Office
San Jose, CA, USA
205K-250K Annually
Senior level
205K-250K Annually
Senior level
Big Data • Information Technology
The Senior Principal Engineering Program Manager will lead ASIC product development, ensuring timely execution, risk management, and cross-functional alignment across various teams to deliver revenue-critical silicon solutions.
Top Skills: AtlassianCosmosCxlEthernetJIRAMs ProjectNvlinkPcieUalink
Reposted 7 Days AgoSaved
In-Office
San Jose, CA, USA
205K-255K Annually
Expert/Leader
205K-255K Annually
Expert/Leader
Big Data • Information Technology
The Senior Principal Technologist will drive the architecture and development of data center memory solutions, engage with customers, and influence product features using expertise in system and memory architecture and technologies.
Top Skills: BiosBmcsCosmos Software SuiteCxlDramEthernetHardware-Software Co-DesignJedecKernelNvlinkOs Software IntegrationPcieSoc MemoryTooling
8 Days AgoSaved
Remote
Germany
Senior level
Senior level
Big Data • Information Technology
Lead architecture and RTL development for high-speed Ethernet and AI scale-up connectivity ASICs. Define microarchitecture, packet processing, DMA/RDMA acceleration, QoS, congestion management, and hardware/software interfaces. Drive designs from architecture through RTL, verification, tapeout, and post-silicon bring-up while mentoring senior engineers and aligning cross-functional teams to performance, power, and manufacturability targets.
Top Skills: AsicCosmos SoftwareCxlDmaDpuEthernetEthernet MacInfinibandNicNvlinkPacket ProcessingPcie Gen6Pcie Gen7Post-Silicon ValidationRdmaRoceRtlSmartnicSocTapeoutUalinkUcie
8 Days AgoSaved
Remote
Germany
Senior level
Senior level
Big Data • Information Technology
Senior technical leader defining ASIC architecture and driving RTL design, verification, tapeout, and post-silicon bring-up for high-performance Ethernet and AI connectivity products. Lead microarchitecture for MACs, NIC datapaths, packet processing, DMA, RDMA/transport acceleration, congestion control, virtualization, and hardware/software interfaces while mentoring teams and meeting performance, power, area, and reliability targets.
Top Skills: AsicCxlDmaDpuEthernetInfinibandNicPciePcie Gen6Pcie Gen7RdmaRoceRtlSmartnicSocUalinkUcie
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Reposted 8 Days AgoSaved
In-Office
San Jose, CA, USA
135K-165K Annually
Mid level
135K-165K Annually
Mid level
Big Data • Information Technology
The Senior Product Engineer will lead high-speed semiconductor product development, overseeing validation, testing, and ATE programming, while ensuring quality delivery to customers.
Top Skills: (Lp)Ddr5/4Advantest 93K AteC/C++CosmosCxlEthernetJmpNrz/Pam4 SerdesNvlinkPciePythonSpotfireUalink
Reposted 8 Days AgoSaved
In-Office
San Jose, CA, USA
158K-220K Annually
Senior level
158K-220K Annually
Senior level
Big Data • Information Technology
Lead product management for Smart Cable Modules, defining product strategy, engaging customers, and ensuring products meet AI infrastructure needs.
Top Skills: Ai InfrastructureCloud ComputingCxlEthernetPcieSemiconductor Technologies
Reposted 8 Days AgoSaved
Remote
California, USA
185K-230K Annually
Senior level
185K-230K Annually
Senior level
Big Data • Information Technology
Lead the functional verification of advanced ASICs, overseeing test planning, execution, and coverage analysis, while collaborating with various teams.
Top Skills: C/C++PythonSystemverilogUvm
Reposted 8 Days AgoSaved
In-Office
San Jose, CA, USA
209K-230K Annually
Senior level
209K-230K Annually
Senior level
Big Data • Information Technology
Design and optimize power delivery systems for ASIC products, ensuring robust integrity and developing board-level designs while collaborating with vendors and teams.
Top Skills: AllegroAsicCadence OrcadDc-Dc ConvertersPcbPower Delivery SystemsVoltage Regulators
Reposted 8 Days AgoSaved
In-Office
San Jose, CA, USA
160K-195K Annually
Senior level
160K-195K Annually
Senior level
Big Data • Information Technology
Lead the development of high-speed semiconductor products, focusing on post-silicon product development, RF testing, and characterizing advanced semiconductor solutions.
Top Skills: Advantest 93K Ate PlatformC/C++CosmosCxlEthernetNvlinkPciePythonRf TestingSpectrum AnalyzersVector Network Analyzers
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