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The Physical Design Manager will lead a team to implement connectivity ASICs, handling execution from RTL to GDSII, while ensuring design quality and mentoring engineers.

The role involves leading Static Timing Analysis for complex AI connectivity silicon, driving methodologies, collaborating cross-functionally, and mentoring engineers.

Lead end-to-end physical implementation of complex multi-die switching products. Build and mentor a large physical design organization, define methodologies for interposer-based chiplet architectures, and drive timing, power, area, and manufacturability to deliver multiple advanced-node tapeouts.

Debug and integrate firmware for Ethernet retimers/gearboxes, triage lab and field failures, fix embedded C/C++ firmware, support customer bring-up, and develop features for SERDES, link training, equalization, and diagnostics.

Lead digital design of high-performance controller and bridge IP from micro-architecture through GDS for advanced-node (≤16nm) SoCs. Own RTL, synthesis, timing closure, verification (UVM), IP integration (processors, peripherals), and pre/post-silicon bring-up and debug, collaborating across teams to ensure first-pass silicon success.

Lead SoC digital design from architecture to GDS for advanced-node (≤16nm) controllers and bridges. Drive RTL development, synthesis, timing closure, IP and peripheral integration (ARM/ARC), UVM verification, pre/post-silicon bring-up and debug, and collaboration across cross-functional teams to ensure first-pass silicon success.

Provide technical guidance to China-region customers on semiconductor product design-in, system bring-up, debugging, and issue resolution. Support PCIe/CXL products, develop technical collateral, coordinate internal engineering teams, and provide product feedback. The role requires expertise in PCIe physical-layer standards, lab equipment, firmware, scripting, data center systems, and customer-facing technical communication in Mandarin.

Define and measure scale-up fabric performance for GPU clusters by building roofline models, benchmarks, and end-to-end workload studies. Run and scale real inference workloads, identify bottlenecks, perform head-to-head comparisons, and build automated test infrastructure. Partner with cross-functional teams to influence architecture, firmware, and product decisions and produce customer-facing performance reports and documentation.

Lead customer-facing technical engagements for Scorpio switch platforms, drive post-silicon validation and system integration, debug complex protocol and SI/firmware issues, mentor engineers, produce technical collateral, and influence product roadmap and feature validation across PCIe Gen6/Gen7, UALink, and related interconnects.

Define, develop, and maintain RTL-to-GDSII physical design flows and automation across Cadence and Synopsys toolchains. Integrate foundry runsets, enable multi-corner/multi-mode STA and EMIR infrastructure, optimize PPA and schedules, build QoR frameworks, and support/scale the PD team through standards, tooling, training, and documentation.