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Reposted 2 Days AgoSaved
In-Office
San Jose, CA, USA
230K-265K Annually
Senior level
230K-265K Annually
Senior level
Big Data • Information Technology
Lead the SIPI engineering team to develop high-performance IC packaging solutions, partner across teams, and drive execution from concept through production.
Top Skills: 3DlayoutAnsys HfssKeysight AdsSiwave
Reposted 2 Days AgoSaved
In-Office
San Jose, CA, USA
200K-250K Annually
Expert/Leader
200K-250K Annually
Expert/Leader
Big Data • Information Technology
Lead global pricing and monetization strategy for semiconductor, software, and connectivity products. Build pricing governance, policies, approval workflows, and pricing models. Partner cross-functionally with Product, Finance, Sales, and Executive Leadership, engage in senior customer negotiations, develop pricing metrics and reporting, and scale a pricing function to support profitable growth and competitive positioning.
Top Skills: CosmosCxlEthernetNvlinkPcieUalink
3 Days AgoSaved
In-Office
San Jose, CA, USA
160K-200K Annually
Entry level
160K-200K Annually
Entry level
Big Data • Information Technology
Lead advanced FCBGA package development from concept through NPI, qualification, and high-volume manufacturing. Manage substrate suppliers and OSAT partners while overseeing schedules, quality, yield, manufacturing readiness, reliability qualification, warpage improvement, and customer quality issues. Drive root cause and failure analysis, corrective actions, and cross-functional execution. Contribute expertise in advanced packaging, including Co-Packaged Optics and Near-Packaged Optics.
Top Skills: Cadence Allegro Package DesignerCo-Packaged Optics (Cpo)FcbgaFlip-Chip PackagingLaminate SubstratesNear-Packaged Optics (Npo)OsatSemiconductor Packaging
3 Days AgoSaved
In-Office
San Jose, CA, USA
160K-200K Annually
Senior level
160K-200K Annually
Senior level
Big Data • Information Technology
Lead RTL design and implementation for complex connectivity silicon blocks from microarchitecture through synthesis sign-off and tapeout. Collaborate with architecture, verification, DFT, and physical design teams on timing closure, lint, CDC, PPA, and silicon readiness. Debug pre- and post-silicon issues, mentor junior engineers, drive design reviews, and contribute to scalable design methodologies. The role focuses on high-speed interconnect technologies including PCIe, CXL, Ethernet, and emerging AI infrastructure interfaces.
Top Skills: 5Nm7NmAssertion-Based VerificationBistCdcCxlDftEmulationEthernetFloorplanningFormal VerificationLintLow-Power DesignPcieRtlScanSocSynthesisSystemverilogTiming ClosureUalinkUcieVerilog
Reposted 3 Days AgoSaved
In-Office
Taipei City, TWN
8-8 Annually
Senior level
8-8 Annually
Senior level
Big Data • Information Technology
Lead Supplier Quality Engineering for semiconductor products, collaborating with suppliers, creating quality data systems, and integrating advanced analytics and AI/ML tools to enhance performance and risk management.
Top Skills: AICosmosCxlEthernetExcelJmpMachine LearningNvlinkPcieSQLUalink
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Reposted 3 Days AgoSaved
Remote
Israel
Expert/Leader
Expert/Leader
Big Data • Information Technology
Lead end-to-end IC package design for high-performance connectivity silicon, owning architecture, layout, SI/PI/thermal tradeoffs, qualification, OSAT engagement, and volume manufacturing readiness from concept through production.
Top Skills: Advanced LaminateBall MapsBgaBump MapsCadence ApdChipletCowosCxlDfmDrcEthernetFcbgaFccspHtolInterposerIpcJedecLvsNvlinkOrganic SubstratesOsatPciePiSerdesSiSipSmtSubstrate RoutingThermal CyclingThermal IntegrityUalink
Reposted 3 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Big Data • Information Technology
Lead the design and execution of functional and performance tests for PCIe switch technology, collaborating with cross-functional teams and mentoring junior engineers.
Top Skills: ConfluenceGitI2CJIRAMctpPciePythonSpdm
Reposted 3 Days AgoSaved
In-Office
San Jose, CA, USA
230K-285K Annually
Expert/Leader
230K-285K Annually
Expert/Leader
Big Data • Information Technology
Lead formal verification strategy and methodology for next-generation connectivity products. Develop formal models, assertions, and test plans; apply EDA tools and complexity-reduction techniques to find corner-case bugs. Mentor global engineers, collaborate with design teams, and represent the company in industry forums.
Top Skills: Assertion-Based Model CheckingCadence JaspergoldCi/CdCxlEda ToolsEthernetPciePerlPythonRtlSynopsys VcformalSystemverilogUalinkUcieVerilog
Reposted 3 Days AgoSaved
Remote
Israel
Senior level
Senior level
Big Data • Information Technology
The Package Design Engineer will lead advanced IC packaging solutions development, executing package design, ensuring manufacturability, and collaborating with multiple teams for high-performance connectivity silicon.
Top Skills: Advanced LaminateCadence ApdCowosCxlEthernetInterposersNvlinkOrganic SubstratesPcieSip
Reposted 3 Days AgoSaved
In-Office
San Jose, CA, USA
187K-260K Annually
Senior level
187K-260K Annually
Senior level
Big Data • Information Technology
Lead product engineering at Astera Labs, driving high-speed semiconductor product development, managing teams, and collaborating on ATE testing and manufacturing.
Top Skills: Advantest 93K Ate PlatformC/C++CxlDdr5EthernetHigh-Speed Serdes ProtocolsJmpLpddr5PciePythonSpotfire
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