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4 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
Seeking a Senior Digital Design Engineer to design and implement high-performance digital solutions, focusing on RTL development and synthesis, collaborating on PCIe/CXL protocols, and ensuring timing closure and verification completeness.
4 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
The Senior Digital Design Engineer will design and implement high-performance digital solutions, focusing on RTL development and synthesis. Responsibilities include collaborating on IP integration, overseeing designs from architecture to GDS, ensuring timing closure, and debugging pre- and post-silicon. The role requires expertise in various design tools and methodologies, along with hands-on processor experience.
4 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
The Principal Digital Design Engineer will design and implement high-performance digital solutions, focusing on RTL development, IP integration, and timing closure. Responsibilities include ownership of block-level and full-chip designs, ensuring verification completeness, and managing pre-and post-silicon debug processes.
4 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
The Principal Digital Design Engineer will design and implement high-performance digital solutions focusing on RTL development and synthesis. Responsibilities include collaborating on IP integration for PCIe/CXL protocols, ensuring timing closure, and overseeing the pre- and post-silicon debug process.
16 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Junior
148 Employees
Junior
Big Data • Information Technology
The Design Verification Engineer will develop and execute verification plans, write and execute test sequences, collaborate with RTL designers to debug issues, and utilize coding expertise for functional verification on PCIe and CXL protocols.
17 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
The Senior Physical Design Engineer will develop and support complex SoC/silicon products for various applications. Responsibilities include using physical design tools, driving designs from architecture to production, collaborating with IP vendors, and ensuring timing closure and formal verification.
17 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
As a Senior DFT Engineer at Astera Labs, you will work on developing next-generation connectivity products, engaging in all product lifecycle stages. Collaboration with various teams is essential, focusing on chip design and DFT techniques such as ATPG and JTAG while ensuring quality through testing and analysis.
17 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
As a Principal DFT Engineer at Astera Labs, you will lead the development of connectivity products, ensuring quality from design to production. This includes collaboration with multiple engineering teams on validation, testing, and analysis of semiconductor solutions.
17 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
The Senior Design Verification Engineer will develop and execute verification plans, write and execute test sequences, collaborate with RTL designers, and analyze coverage data. Responsibilities include using coding expertise for functional verification and creating VIP abstraction layers for simplified verification processes.
17 Days Ago
Bengaluru, Karnataka, IND
148 Employees
Expert/Leader
148 Employees
Expert/Leader
Big Data • Information Technology
As a Principal Physical Design Engineer, you will lead complex SoC/silicon product designs for Server, Storage, and Networking applications. You will be responsible for full chip or block level ownership, synthesis, timing closure, and verification, while utilizing backend tools and methodologies.
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