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Lead sourcing strategy for silicon supply chain categories (Foundry, OSAT, Substrates, Test). Develop should-cost and TCO models, negotiate complex agreements, manage supplier relationships and SRM programs, assess supplier financials and IP, and align sourcing with R&D roadmaps to ensure cost savings, risk mitigation, and business continuity for scale-up AI connectivity products.

The Principal Product Application Engineer will lead firmware development and customer engagement for CXL Smart Memory Controllers, ensuring seamless integration and resolution of firmware issues while collaborating with various engineering teams.

The Principal Emulation Engineer will verify protocols on ASICs, create testing environments, and debug hardware-software interfaces, focusing on communication protocols like PCIe and Ethernet.

Lead the development of AI-powered IP Lifecycle and Quality Assurance Platform, ensuring all IP meets integration standards, through advanced EDA tools and automated audits.

The Senior VLSI Design Engineer will design and implement digital blocks for complex semiconductor chips, tackling logic challenges and ensuring robust performance in AI infrastructure solutions.

As a Senior Physical Design Engineer, you will oversee the physical implementation of complex semiconductor designs and guarantee their performance and integrity.

Senior Design Verification Engineer responsible for developing and executing UVM/SystemVerilog verification environments, integrating C/C++ via DPI/PLI, creating constrained-random tests, writing assertions and coverage, using third-party VIPs (PCIe, Ethernet, NVMe, DDR, etc.), automating infrastructure with scripting, and collaborating with RTL designers to debug SoC silicon for server, storage, and networking applications.

Lead design verification for complex SoC/silicon products using UVM and C/C++-based environments. Develop UVM testplans, constrained-random stimuli, assertions and coverage, integrate C/C++ via DPI/PLI, automate infrastructure with scripting, use 3rd-party VIPs (PCIe, Ethernet, InfiniBand, DDR, NVMe, USB), and collaborate with RTL designers to debug in simulation, co-simulation, and emulation.

The job involves defining product requirements, engaging with customers, and collaborating with teams to deliver semiconductor products for AI infrastructure.

The Senior Emulation Engineer will execute emulation flows, debug and validate semiconductor chips, and collaborate with cross-functional teams to enhance hardware-software integration.