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Leads and grows the ATE Test Engineering organization, defining test strategies for high-speed mixed-signal and SoC products from silicon bring-up through high-volume manufacturing. Oversees wafer-sort and final-test hardware, ATE program development, characterization, debug, coverage, yield, cost, and test-time optimization. Partners with design, DFT, product engineering, operations, and manufacturing teams to deliver production-ready connectivity products and improve quality and execution.

Leads complex analog/mixed-signal semiconductor programs from specification through tape-out and silicon validation. Responsibilities include developing schedules, managing milestones, budgets, dependencies, risks, and deliverables; coordinating circuit design, layout, verification, validation, systems, operations, foundries, and vendors; leading program reviews; communicating status and trade-offs; and improving program management processes.

Develop and execute block- and system-level verification plans for complex SoC and silicon designs using PCIe and CXL protocols. Create UVM test sequences, assertions, cover properties, randomized constraints, and VIP abstraction layers. Analyze coverage and system-level performance, debug failures with RTL designers, and verify Physical, Link, and Transaction Layers across PCIe/CXL endpoint and root-complex implementations.

Leads hardware emulation strategy and execution for complex ASIC, SoC, and IP designs. Develops emulation environments, brings up RTL, creates verification plans and transactors, optimizes compilation and runtime performance, and debugs issues across RTL, testbenches, emulation platforms, and software. Enables early firmware and software validation, supports pre- and post-silicon debug, automates regressions, improves methodologies, and mentors engineers during major IP and SoC bring-up milestones.

Provide customer-facing technical support for semiconductor products, lead silicon and system bring-up, validation, and debug in lab and customer environments, develop technical collateral, collaborate with cross-functional teams to resolve integration issues, and provide product/process feedback to improve solutions and workflows.

Leads mechanical architecture and system integration for rack-scale AI infrastructure, GPU platforms, networking systems, optical connectivity, and air- or liquid-cooled systems. Defines rack layouts, mechanical interfaces, packaging, cable management, cooling integration, manufacturability, serviceability, and design requirements. Collaborates with electrical, thermal, power, silicon, software, manufacturing, product, and ODM teams to drive system integration, validation, cost optimization, and production readiness.

The Senior Firmware Engineer will architect and develop firmware for SoC and systems, working with hardware and ensuring customer needs are understood and met.

The Principal Test Engineer will develop SoC test strategies, lead ATE solutions, and ensure high volume production quality through collaboration with manufacturing partners.

Lead the development of high-speed semiconductor products, focusing on post-silicon product development, RF testing, and characterizing advanced semiconductor solutions.

Own immigration case management end-to-end, manage external immigration service providers, and lead cross-functional HR operations projects. Build and document SOPs, dashboards, and automated workflows using Microsoft tools. Partner with HR, Legal, Talent Acquisition, IT, and Finance to ensure compliant, scalable processes and strong stakeholder communication.