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Lead functional verification for advanced ASICs and SoCs, including test planning, SystemVerilog/UVM development, constrained-random testing, debugging, coverage analysis, and coverage closure. Collaborate with RTL designers, software teams, and system validation teams on emulation and hardware-software co-verification. Drive verification methodologies for server and networking applications, including switching architectures, packet processing, PCIe, Ethernet, and NoC designs.

Leads the Toronto physical design engineering team and owns ASIC implementation from RTL through GDSII and tapeout. Responsibilities include floorplanning, place-and-route, CTS, timing closure, extraction, EM-IR, DRC/LVS, equivalence checking, IP integration, methodology development, cross-functional convergence, hiring, mentoring, and coordination with global physical design teams. The role focuses on high-speed connectivity ASICs, including retimers and signal-conditioning products, using advanced-node semiconductor technologies.

Leads strategic sourcing across semiconductor supply-chain categories including foundries, OSATs, substrates, and test providers. Develops category strategies, analyzes supplier capabilities and costs, builds should-cost and TCO models, negotiates complex agreements, manages supplier relationships, mitigates supply risk, and aligns sourcing decisions with technology roadmaps. Partners with engineering, R&D, and global stakeholders to support product development, capacity, cost savings, supplier performance, and business continuity.

Owns full-chip and block-level physical design from architecture through GDSII and production. Responsibilities include synthesis, place and route, clock tree synthesis, timing closure, formal equivalence verification, physical verification, DFT, ECO implementation, and collaboration with RTL and hard-macro IP vendors. The role supports complex SoC and silicon products for server, storage, and networking applications using advanced process technologies.

Design, develop, and deploy LLM-powered agentic applications for RTL, physical and analog design, linting, static analysis, and formal verification. Build engineering assistants, dialogue systems, retrieval infrastructure, databases, and dashboards integrated with CAD/EDA workflows. Collaborate with hardware design, design verification, formal verification, and CAD teams to identify challenges and deliver AI-assisted tools. Apply software engineering and AI/ML expertise to accelerate debugging, coverage closure, lint analysis, RTL optimization, and formal proof convergence.

Leads end-to-end engineering programs for analog/mixed-signal semiconductor IP, from specification through tape-out and silicon validation. Coordinates circuit design, layout, verification, systems, product, operations, foundries, and vendors. Owns schedules, milestones, budgets, metrics, risks, stakeholder communication, and program reviews while driving process improvements and resolving cross-functional blockers.

Lead the end-to-end development and technical direction of internal automation platforms. Build full-stack features, backend services, frontend interfaces, databases, access controls, approval workflows, dashboards, and integrations with SaaS, cloud, and identity systems. Automate IT, HR, and Finance workflows involving onboarding, offboarding, asset tracking, entitlements, audit logging, and access reviews. Personally write code, evolve schemas, maintain testing, establish engineering standards, and use AI-assisted development tools.

Architects and develops firmware and microcontroller subsystems for SoC and systems products. Responsibilities include C/C++ firmware and SDK development, Python scripting, HW-SW interface implementation and testing, unit testing, build automation, source control, CI workflows, and collaboration with hardware designers and customers. Preferred work includes RTOS, boot ROM, pre-silicon simulation and emulation, and secure boot technologies.

Own RTL synthesis, SDC constraint development, MMMC setup, and STA timing closure for high-speed SerDes digital and mixed-signal ASIC designs. Optimize area, power, and timing; manage advanced-node signoff, timing budgets, ECOs, hierarchical analysis, and clock/power-domain strategies. Collaborate with analog, RTL, physical design, verification, and architecture teams to achieve block- and full-chip timing convergence.

Leads and develops a US-based technical program management team responsible for advanced ASIC programs from architecture through production release. Oversees milestone planning, dependencies, execution reviews, risk mitigation, budgeting, resource allocation, and readiness for tapeout, power-on, validation, qualification, and manufacturing. Partners with engineering, executives, customers, and external partners while driving consistent reporting, accountability, and cross-functional issue resolution.