Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Physical Design Engineering Director to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers.
As an Physical Design Engineering Director, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.
Basic Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
- 15+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
- 5+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
- Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
- Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
- Strong scripting ability in Tcl, Python, and/or Perl.
- Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
Required Experience
- Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
- Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
- Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
- Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
- Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
- Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
- Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
- Experience with Cadence and/or Synopsys physical design tools/flows.
Preferred Experience/Nice to Have
- Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
- Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
- Track record of building and scaling physical design teams through multiple tapeouts.
- Knowledge of agentic AI solutions for EDA automation.
Base salary range is CAD 200,000 to CAD 250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 15+ years of experience in physical design implementation of complex SoCs at advanced nodes, 7nm and below
- 5+ years of experience leading teams or projects
- Hands-on expertise in synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking
- Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler or ICC2
- Strong scripting ability in Tcl, Python, and/or Perl
- Ability to build, lead, mentor, hire, and develop a physical design team
- Experience driving block and top-level physical design from floorplan through tapeout
- Experience collaborating with RTL, DFT, STA, EMIR, and verification teams
- Experience integrating RTL and hard-macro IP from vendors
- Experience establishing physical design best practices, flow improvements, and quality checks
- Experience coordinating with global physical design teams
- Master's degree
- Understanding of high-speed SerDes physical layers, equalization, CDR, and signal integrity
- Knowledge of physical-layer timing challenges for high-speed serial interfaces
- Track record of scaling physical design teams through multiple tapeouts
- Knowledge of agentic AI solutions for EDA automation
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
