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Develops pre-silicon RTL verification for PCI Express controller technologies. Responsibilities include creating testbenches and sequences, planning and coding functional coverage, expanding regression suites, monitoring and debugging regressions, triaging RTL and environment issues, and supporting verification scripting capabilities. The role requires SystemVerilog/UVM and Verilog/RTL experience, with Python and Tcl scripting preferred. It is a hybrid position with at least three onsite days weekly in Bengaluru.

Leads technical marketing for Rambus memory interface chip products, including product positioning, requirements development, technical collateral, ecosystem enablement, standards engagement, customer communications, training, and competitive analysis. Serves as the technical liaison among engineering, product management, sales, customers, processor vendors, SoC companies, memory suppliers, and industry partners. Supports product launches, qualification activities, customer issue resolution, and evaluation of future memory technologies such as DDR6 and MRDIMM.

Supports customer and supplier quality for semiconductor products by reviewing requirements, coordinating audits, managing new product approvals, flowing down supplier requirements, monitoring supplier quality, and driving corrective actions and continuous improvement. The role serves as a primary customer contact and collaborates with internal teams and suppliers to resolve quality issues and ensure compliance with Rambus and customer requirements.

Lead semiconductor new product introduction from project kickoff through production and sustaining support. Define test coverage, characterization, qualification, schedules, resources, and infrastructure; coordinate with internal teams, customers, suppliers, wafer foundries, and OSAT partners. Support product lifecycle management, failure analysis, RMA activities, yield and cost optimization, and high-volume manufacturing bring-up. Apply data analysis to improve cycle time and quality.

Leads pre-silicon RTL verification for PCIe and CXL controller IP. Develops SystemVerilog/UVM testbenches and sequences, plans and implements functional coverage, expands regression suites, monitors and debugs regressions, triages RTL and test-environment issues, and supports verification scripting capabilities.

Lead DFT development for high-speed mixed-signal PMIC and SoC designs, including DFT IP creation, scan compression, ATPG, coverage analysis, silicon debug, pattern development, and flow deployment. Collaborate with design, verification, test engineering, and EDA teams on DFT architecture, constraints, yield improvement, silicon bring-up, and new methodology implementation.

Design and develop next-generation PCIe, CXL, and AMBA controller IPs. Responsibilities include architecture and micro-architecture, SystemVerilog RTL implementation, collaboration with verification teams, and FPGA prototyping. The role requires close collaboration with international engineering teams in a hybrid work environment.

Leads analog and mixed-signal circuit design for high-performance memory interface chips. Responsibilities include architecture definition, circuit design and simulation, modeling, floorplanning, post-extraction analysis, verification, post-silicon validation, debugging, and customer collaboration. The role also mentors junior engineers and drives cross-functional work across the full chip development lifecycle, from concept through volume production.

Develops and maintains verification environments for PCIe and CXL controller IP. Responsibilities include testbench and sequence development, functional coverage planning, regression testing, failure triage, RTL debug, and verification scripting. The role requires strong SystemVerilog, UVM, Verilog, RTL, and PCI Express expertise, with Python and Tcl scripting preferred. This is a hybrid, onsite-oriented position in Bengaluru, India.

Design and architect hardware systems, perform trade-off analysis, develop and verify RTL, integrate and verify memory controllers and PHYs, and support customer deliveries. The role requires ASIC or FPGA design expertise, scripting and simulation experience, and collaboration with engineering and customer teams. Preferred experience includes synthesis, timing constraints, CDC/RDC, memory technologies, and AMBA protocols.