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Acts as the technical interface between internal engineering teams and foundry partners. Drives semiconductor yield improvement, root-cause investigations, process enhancements, technology qualification, tapeout execution, engineering lot planning, and high-volume production readiness. Supports new-node and foundry evaluations, wafer WIP management, and interpretation of PDKs, design rules, and process guidelines. Requires semiconductor process technology expertise, foundry interaction experience, TSMC familiarity, and fluency in English and Mandarin.

Develop and execute verification plans for high-speed DDR memory interface chips, from design requirements through verification sign-off. Build UVM-based testbenches and verification infrastructure for complex blocks, IP, and subsystems; debug issues; collaborate with architects, designers, and post-silicon teams; and mentor engineers toward closure.

Lead analog and mixed-signal circuit design for high-performance memory interface chips, including architecture, simulation, modeling, floorplanning, verification, post-silicon validation, debugging, and customer collaboration. The role owns chip- and block-level designs, supports production development, and mentors junior engineers across globally distributed teams.

Lead semiconductor product engineering for new product introductions from kickoff through production and sustaining support. Define test coverage, characterization, qualification, schedules, and resources; coordinate cross-functional teams, customers, suppliers, foundries, and OSAT partners. Support wafer sort, final test, failure analysis, RMA activities, yield and quality optimization, and high-volume manufacturing. Apply expertise in analog, mixed-signal, power, DDR, and high-speed digital products, along with C/C++, Linux, ATE, and data-analysis tools.

Designs and architects next-generation PCIe intellectual property, develops RTL in Verilog and SystemVerilog, collaborates with verification teams, prototypes designs on FPGAs, and supports existing IP generations. The role requires advanced electrical or computer engineering education, extensive RTL design experience, strong communication skills, and preferably knowledge of PCIe or CXL standards.

Develops and executes growth plans for strategic semiconductor and silicon IP accounts. The role owns revenue, gross margin, design-win, forecasting, account expansion, and new-account acquisition goals. It builds senior customer relationships, assesses market opportunities, partners with marketing and business units on account strategies, identifies customer and market requirements, and supports new product launches.

Develops and maintains pre-silicon RTL verification environments for PCIe and CXL controller IP. Responsibilities include testbench and test-sequence development, functional coverage planning, regression execution and triage, RTL debug, and verification scripting. The role requires SystemVerilog/UVM, Verilog, RTL, and scripting experience, with PCIe or other I/O controller familiarity preferred. This is a hybrid position based in Sofia, Bulgaria, with an expectation of approximately three onsite days per week.

Design and verify PCIe controller soft IP and PHY integrations through pre-silicon RTL development, simulation, and FPGA prototyping. Develop verification test cases, support customer IP integration, improve verification processes, maintain requirements traceability, track productivity metrics, and report project progress. Collaborate with international teams and provide customer support for complex ASIC/VLSI verification activities.

Lead the architecture, design, implementation, verification, and release of secure silicon IP. Responsibilities include leading digital designers, specifying blocks, developing RTL, performing lint, CDC analysis and synthesis, debugging simulations, supporting formal verification, improving design methodologies, and coordinating with technical, product, sales, and field engineering teams.

Lead the architecture, RTL design, integration, validation, debugging, and delivery of complex memory controller silicon IP. Collaborate with architecture, verification, implementation, product, customers, and field teams; resolve technical issues; guide engineering tradeoffs; improve quality and coverage; and mentor engineers throughout the product lifecycle.