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Designs and implements SystemVerilog and Verilog RTL for DDR5 and DDR6 memory interface products. Responsibilities include block integration, simulation, PPA analysis, timing improvement, functional modeling, design quality checks, verification debugging, documentation, and chip power-on validation. Collaborates with digital, analog, physical design, verification, validation, and product qualification teams.

Leads sourcing strategy for semiconductor foundry and OSAT suppliers, including supplier negotiations, performance monitoring, cost analysis, long-term planning, procurement initiatives, and process improvements. The role manages supply, quality, technology, and cost objectives; supports budgeting and cash-flow activities; drives supplier performance and savings programs; and serves as a procurement consultant for internal and external partners.

Designs, verifies, integrates, tests, and supports memory controller silicon IP. Responsibilities include preparing IP deliveries, integrating third-party IP, debugging simulation failures, developing new RTL functionality, and providing customer support.

Architects high-performance PCIe controller silicon IP for data center and AI applications. Owns architecture specifications, drives technical reviews, collaborates with design, verification, physical design, product, marketing, field, and customer teams, represents the company at PCI-SIG, supports technical presales and customer solutions, develops patents and publications, and trains field teams.

Develop and execute semiconductor test plans across product development, prototypes, high-volume manufacturing, and sustaining support. Design ATE hardware, improve test coverage and yield, optimize test time and multisite performance, debug test patterns, tune timing and levels, and collaborate with design teams, customers, suppliers, and OSAT partners. The role focuses on Advantest V93k-based testing of integrated circuits, preferably including DDR and high-speed digital products.

Lead verification for high-speed DDR memory interface chips from requirements through sign-off. Develop test plans, tests, and UVM-based verification infrastructure for complex blocks, IP, and subsystems. Build testbench architectures, debug issues, guide team members, collaborate with architects, designers, and post-silicon validation teams, and support validation after tapeout.

Develop test plans and coverage for semiconductor products, design ATE hardware for new product introduction, and support products through prototyping, high-volume manufacturing, and sustaining operations. Optimize yield, test time, and multisite testing while collaborating with design teams, customers, suppliers, and offshore OSAT partners. The role requires expertise with Advantest V93k and familiarity with DFT methodologies, Smartest, Red Hat, and version-control tools.

Leads signal and power integrity modeling, simulation, package design, and system-level analysis for high-speed DDR memory products. Defines packaging, PCB routing, decoupling, channel, jitter, and SI/PI requirements; correlates simulations with laboratory measurements; supports debugging and product bring-up; collaborates with design, validation, customers, and cross-functional teams to optimize performance.

Own chip-level layout collaterals and design assigned blocks using Cadence Virtuoso XL/VXL. Perform Calibre LVS, DRC, antenna, and density verification; resolve reliability issues including EMIR and ESD/latchup. Collaborate with analog designers globally on matching, parasitics, noise isolation, shielding, wells, substrates, and layout-dependent effects. The role requires semiconductor device physics knowledge, advanced-node layout experience, and familiarity with scripting.

Acts as the technical interface between internal engineering teams and foundry partners. Drives semiconductor yield improvement, root-cause investigations, process enhancements, technology qualification, tapeout execution, engineering lot planning, and high-volume production readiness. Supports new-node and foundry evaluations, wafer WIP management, and interpretation of PDKs, design rules, and process guidelines. Requires semiconductor process technology expertise, foundry interaction experience, TSMC familiarity, and fluency in English and Mandarin.