Top Tech Jobs & Startup Jobs

Develop and validate bench and system environments for DDR5 enablement devices, ensuring performance specification compliance. Responsibilities include characterizing I2C/I3C protocols, automating laboratory testing with Python, supporting customers, and providing post-silicon bring-up support while coordinating with design, operations, and development teams.

Leads the architecture, RTL design, integration, validation, debugging, and delivery of complex memory controller silicon IP. Collaborates with architecture, verification, implementation, product, customer, and field teams; defines microarchitecture and design tradeoffs; supports customer integration; and mentors engineers while ensuring high-quality production releases.

Leads end-to-end global semiconductor operations, including foundry and OSAT management, materials strategy, planning, logistics, NPI and production ramp, supply continuity, risk mitigation, cost reduction, and productivity improvement. Builds resilient operations organizations, establishes governance and business continuity plans, manages supplier relationships, and partners cross-functionally to optimize delivery, revenue, margin, and operational performance.

Architect and develop secure ASIC and silicon IP, including post-quantum cryptography accelerators, random number generators, and cryptographic cores. Responsibilities include researching security techniques, contributing to architecture and design, collaborating with software and security teams, supporting product certification, improving quality and safety, and ensuring compliance with engineering standards. The role requires digital design and front-end ASIC expertise, with knowledge of cryptography, side-channel attacks, back-end flows, DFT, and hardware development in Unix/Linux environments.

Lead microarchitecture and RTL design for high-performance memory controller blocks. Analyze power, performance, and area tradeoffs; collaborate with verification and physical design teams; debug regressions and timing, power, and congestion issues; and support customer pre-sales and post-sales engagements.

Design and verify pre-silicon RTL for PCIe and CXL controller soft IP and PHY integrations. Responsibilities include Verilog RTL design, simulation-based IP integration verification, test-case development, customer integration support, verification-process improvements, requirements traceability, productivity metrics, and progress reporting. The role collaborates with international teams and may require travel abroad.

Own microarchitecture and RTL design for high-performance memory controller blocks. Analyze performance, power, and area tradeoffs; collaborate with verification and physical design teams; debug regressions and resolve timing, power, and congestion issues. Provide technical support for pre-sales customer engagements and post-sales deliveries. The role requires extensive ASIC/FPGA logic design experience and expertise in SystemVerilog or Verilog, simulation tools, and scripting.

Designs microarchitecture and RTL for high-performance memory controller blocks, analyzes performance, power, and area trade-offs, collaborates with verification and physical design teams, debugs regression failures, and supports customer engagements. The role requires extensive ASIC or FPGA logic design expertise, simulator and scripting experience, and offers opportunities to work with advanced memory technologies and interfaces.

Leads pre-silicon RTL verification for PCIe and CXL controller IP. Develops UVM/SystemVerilog testbenches and sequences, plans and implements functional coverage, augments regression suites, monitors and debugs regressions, triages RTL and test-environment issues, and develops verification scripting capabilities.

Develops pre-silicon RTL verification for memory controller IP supporting DDR, HBM, and GDDR technologies. Responsibilities include testbench and test-sequence development, functional coverage planning, regression testing, debug and triage, RTL issue analysis, and verification-environment scripting. The role requires expertise in SystemVerilog and Verilog, with Python and Tcl scripting preferred, plus substantial design-verification experience.