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The role involves hands-on SOC design implementation, focusing on areas like datapath design, low power design, and ASIC macro/micro-architecture. Responsibilities include mentoring, defining design requirements, evaluating trade-offs, and improving design quality across teams.

The Senior Engineer in Failure Analysis Engineering will lead advanced electrical failure analysis for hard disk drives, identify root causes through data analysis, and provide conclusions for engineering changes. The role will also participate in teams focused on cost and quality improvements.

The Senior Manager - ASIC Development Engineering (DFT) will lead DFT architecture definitions for SoC development, provide solutions for complex DFT challenges, collaborate with cross-functional teams on DFT requirements, and guide design and testing teams on methodologies and requirements. They will also drive improvements in DFT methodology based on silicon debugging insights.